1、Beginner VHDLTraining Class VHDL初学者入门,Danny MokAltera HK FAE(),Lucky Sun 译,What is VHDL(什么是VHDL),Very high speed integrated Hardware Description Language (VHDL) 超高速集成硬件描述语言is an industry standard hardware description languagedescription the hardware in language instead of graphiceasy to modify 是一种工业
2、标准硬件描述语言; 用语言 easy to maintain 代替图形描述硬件;易修改;易维护very good for 非常适合于complex combinational logic 复杂组合逻辑BCD to 7 Segment converter BCD-七段码转换器address decoding 地址解码state machine 确定机器状态more than you want.更多你想做的,What VHDL Standard means?(VHDL 标准的含义),The VHDL is used to describe VHDL用于描述Inputs port -输入口Outpu
3、ts port -输出口behavior and functions of the circuits 电路的状态和功能The language is defined by two successive standardsIEEE Std 1076-1987 (called VHDL 1987)IEEE Std 1076-1993 (called VHDL 1993)该语言由上述两种标准连续定义,Altera VHDL,Altera Max+Plus II support both VHDL 1987 and 1993 (ALTERA MAX+PLUSII 支持上两种标准)Max+Plus II
4、 only support SUBSET of the two IEEE standard(MAX+PLUSII 仅支持两个IEEE标准的子集)Detail of the support can be referred to Altera Max+Plus II VHDL handbook on page 89 Section 3 (支持的细节请参考Max+Plus II VHDL 手册89页3段),How to use the VHDL 如何使用VHDL,use any text editor to create the file 用任意文本编辑器建立文件Altera Software Ma
5、x+Plus II provides text editor ALTERA软件也有文本编辑器,建立自己的VHDL文件,create your VHDL file,把你的文件存为name.VHD,save your VHDL file as name.VHD,选择VHDL标准版编码,Select the Standard Version of VHDL coding1987 or 1993,编译你的VHDL文件,Compile your VHDL file,DONE ! 完成!,Bonus Topic may help forVHDL DesignwithinMax+Plus II,MAX+PL
6、USII中的获奖论文有助于VHDL设计,Turn on some Max+Plus II Option启用选择项,There are some built-in Option to assist the engineer during the VHDL design stage一些内部选项可帮助设计Syntax Color Option from the Option menu选择菜单中的语句颜色选择,Turn onthis option选定此项,Reserve word in Blue 语句变为蓝色,User can modify the Color Option用户能修改颜色,use th
7、e Color Palette under Option Menu to customize the color of 在选择菜单下用调色板设定颜色comments, illegal characters, megafunctions, macrofuncitons. 注释,非法字符,多功能,宏功能,Error Location during Compilation编译时定位错误,Easy to locate the error 很容易确定错误的位置,VHDL Template 模版,General VHDL Format 普通VHDL格式,ENTITY test ISPORT ( input
8、_pin_name : IN bit; output_pin_name : OUT bit);END test;ARCHITECTURE test_body OF test ISBEGINoutput_pin_name = input_pin_name;END test_body;,Your First VHDL design - 2 input AND gate 自己的第一个设计2输入端与门,Entity simand isPort ( a, b : in bit; c : out bit);end simand;architecture simand_body of simand isbe
9、ginc = a and b;end simand_body;,More detail 细节内容,Why I use VHDL instead of Graphic 我为什么用VHDL取代图形,Easy to Modify 容易修改It is more powerful than Graphic 功能比图形更强大VHDL is a portable language because 称VHDL为便携式语言是因为is device independent 不依赖于设备the same code can be applied to Device manufactured by Company A
10、or Company B 相同的代码可以用于甲公司的设备 也可用于乙公司的设备,图形与VHDL对比,Graphic vs VHDLGraphic is what you draw is what you get 图形：需要什么画什么“ tell me what hardware you want and I will give it to you”“告诉我你要什么样的硬件，我会给你的”VHDL is what you write is what functional you getVHDL ：把你需要的功能写出来“ tell me how your circuit should behave
11、and the VHDL compiler will give you the hardware that does the job”告诉我你的硬件如何工作，VHDL编译器会让硬件去做 but the designer can not control how the circuit implement但是设计者不能控制电路的工作,Learning VHDL must learn学习VHDL前要知道,What is Combinatorial Logic 什么是组合逻辑What is Sequential Logic 什么是顺序逻辑What is Concurrent Statement 什么是
12、并行描述What is Process Statement 什么是过程描述,Combinatorial Logic 组合逻辑,Combinatorial Logic if 组合逻辑的工作状态Outputs at a specified time are a function only of the inputs at that time 指定时刻的输出仅为此时输入的一个功能e.g. decoders, multiplexes and adders 如解码器，多路器，加法器,Sequential Logic 顺序逻辑,Sequential Logic if 顺序逻辑的工作状态Outputs at
13、 a specified time are a function of the inputs at that time and at all preceding times 指定时刻的输出是输入在此时及之前的功能All sequential circuits must include one or more registers顺序电路必有一个以上寄存器。如状态机，计数器，移位寄存器，控制器e.g. State Machine, Counters, Shift Register and Controllers,现在大家应该知道了什么是,Now everyone should know what
14、isCombinational Logic 组合逻辑Sequential Logic 顺序逻辑Q : Then how about Concurrent or Process Statement ? What is it ?问题：什么是并行描述和过程描述？,Concurrent Statement 并行描述,All the Concurrent Statement is executed in parallel 并行描述都是：可以同时工作的Concurrent Statement does not care the position within the coding 与在程序中的书写位置无关
15、Concurrent Statement is : OUTPUT depends on INPUT only 输出仅与输入有关,Entity test1 IsPort ( a, b : in bit; c, d : out bit);end test1;architecture test1_body of test1 isbeginc = a and b;d = a or b;end test1_body;,Entity test1 IsPort ( a, b : in bit; c, d : out bit);end test1;architecture test1_body of test
16、1 isbegind = a or b;c = a and b;end test1_body;,THE SAME执行时一样,C = A and B,D = A OR B,c = a and b;d = a or b;,d = a or b;c = a and b;,Process Statement,All the Process Statement is executed in parallelsequential所有过程描述都是并行执行的Within the Process Statement, the coding is execute in sequential在过程描述内，代码是顺序
17、执行的Process Statement is : OUTPUT depends on INPUT with Sensitivity List to control the event happen输出取决于与敏感度表有关的输入，敏感度表控制事件的发生,Entity test1 isPort ( clk, d1, d2 : in bit; q1, q2 : out bit);end test1;architecture test1_body of test1 isbeginProcess (clk, d1)beginif (clkevent and clk = 1) thenq1 = d1;e
18、nd if;end process;Process (clk, d2)beginif (clkevent and clk= 1) thenq2 = d2;end if;end process;end test1_body;,Entity test1 isPort ( clk, d1, d2 : in bit; q1, q2 : out bit);end test1;architecture test1_body of test1 isbeginProcess (clk, d2)beginif (clkevent and clk = 1) thenq2 = d2;end if;end proce
19、ss;Process (clk, d1)beginif (clkevent and clk= 1) thenq1 = d1;end if;end process;end test1_body;,The two process statement execute in parallel这两个过程描述并行执行,Now, I know what is 现在，我们知道了什么是combinational logic 组合逻辑sequential logic 顺序逻辑concurrent statement 并行描述process statement 过程描述Q : What is the usage o
20、f this in VHDL ?问：它们在VHDL中怎么用？A : Engineer can use the mixture of 答：工程师可混合使用这些内容combinational logic, sequential logic, concurrent statement and process statementto do the design 来进行设计,How to . ? 关于?,Now I know what is Combinational Logic but?Q : How to implement of Combinational Logic in VHDL?问:在VHD
21、L中如何实现组合逻辑Combinational Logic can be implemented by 可实现,通过Concurrent Signal Assigment Statements并行信号分配描述Process Statement that describe purely combinational behaviour i.e. behaviour that does not depends on any CLOCK EDGE过程描述纯粹表达组合行为，即与任何CLOCK EDGE无关的行为,Concurrent StatementsforCombinational Logic,组合
22、逻辑中的并行描述,Concurrent Statements 并行描述,There are several different kinds of Concurrent Statements几种不同类型的并行描述(1) Simple Signal Assigments 简单信号分配(2) Conditional Signal Assigments 条件信号分配(3) Selected Signal Assignments 选择信号分配,(1) Simple Signal Assigment 简单信号分配,These kind of statements are executed in Paral
23、lel这种描述是并行执行的,Entity test1 isport ( a, b, e : in bit; c, d : out bit);end test1;architecture test1_body of test1 isbeginc = a and b;d = e;end test1_body;,What kind of logic support l逻辑运算种类,AND 与NAND 与非OR 或NOR 或非XOR 异或NOT 非more .更多,I want 5 Input AND Gate设计5输入与门,Q :AND is only a two input, if I want
24、more input, what can I do ?A : It is easy, we are due with Language not Graphic问：与门只有两个输入，如果想要更多的 输入怎么办？答：好办。用语句就可实现。,Entity test1 isport ( a, b, c, d, e : in bit; f : out bit);end test1;architecture test1_body of test1 isbeginf = a and b and c and d and e;end test1_body;,LAB 1实验1,Design a 7 Input O
25、R gate设计7输入端或门,Sampling Coding代码示例,Entity test1 isport ( a, b, c, d, e, f, g : in bit; h : out bit);end test1;architecture test1_body of test1 isbeginh = a or b or c or d or e or f or g;end test1_body;,(2) Conditional Signal Assigments条件信号分配,The output get the value when the condition is true条件为真时则有
26、输出e.g. 2 to 1 multiplexer 如 2选1多路开关,Entity test1 isport (in1, in2, sel : in bit; d : out bit);end test1;architecture test1_body of test1 isbegind = in1 when sel = 0 else in2;end test1_body;,If I want more - 4 to 1 Mux 输入增加，4选1多路开关,Once again, you are due with Language not Graphic, so it is easy 由于使用
27、语句完成，很容易实现,Entity test1 isport (in1, in2, in3, in4 : in bit; sel1, sel2 : in bit; d : out bit);end test1;architecture test1_body of test1 isbegind = in1 when sel1 = 0 and sel2 = 0 else in2 when sel1 = 0 and sel2 = 1 else in3 when sel1 = 1 and sel2 = 0 else in4;end test1_body;,(3) Select Signal Assig
28、nments选择信号分配,The output get value when matching with the selected item当与选择条件匹配时产生输出,Entity test1 isport (a, b: in bit; sel : in bit; c : out bit);end test1;architecture test1_body of test1 isbeginwith sel select c = a when 1, b when 0;end test1_body;,If I want more choice - 如果选项增多时,It is easy 也很容易,E
29、ntity test1 isport (in1, in2, in3, in4 : in bit; sel : in integer; out1 : out bit);end test1;architecture test1_body of test1 isbeginwith sel select out1 = in1 when 0, in2 when 1, in3 when 2, in4 when 3;end test1_body;,LAB 2实验2,Convert the design from Graphic to VHDL从图形向VHDL转换设计,Design Constraint 设计
30、限制,Use the WHEN-ELSE statement to finish your design用WHEN-ELSE 语句完成你的设计,100,010,001,other,Sampling Coding 代码示例,Entity test1 isport (high, medium, low : in bit; highest_level3, highest_level2 : out bit; highest_level1, highest_level0 : out bit);end test1;architecture test1_body of test1 isbeginhighes
31、t_level3 = 1 when high=1 and medium=0 and low=0 else 0;highest_level2 = 1 when high=0 and medium=1 and low=0 else 0;highest_level1 = 1 when high=0 and medium=0 and low=1 else 0; highest_level0 = 0 when high=1 and medium=0 and low=0 else 0 when high=0 and medium=1 and low=0 else 0 when high=0 and med
32、ium=0 and low=1 else 1;end test1_body;,Simulation 模拟运行结果,Process StatementforCombinational Logic,组合逻辑中的过程描述,Process Statement 过程描述,There are some rules for the Process Statement usage 使用过程描述的一些规则any kind of Process Statement must have SENITIVITY LIST过程描述中必须有敏感度表sensitivity list contains the signals
33、that cause the process statement to execute if their values change敏感度表中的信号，当其值变化时使过程描述执行the statement within the Process Statement will be execute STEP-BY-STEP 过程描述中的语句是一条接一条执行Q : What does it all means ? 问：这意味着什么?A : Follow me.答：接着听.,Template for Process Statement过程描述的模版,Using the “SENSITIVITY LIST
34、”name : PROCESS (sensitivity_list)begin sequential statement #1 sequential statement #2 . sequential statement # NEND PROCESS name;,Example will be more clear用实例更清楚,Entity test1 isport (a, b, sel1, sel2 : in bit; result : out bit);end test1;architecture test1_body of test1 isbeginprocess (sel1, sel2
35、,a, b)beginif (sel1 = 1) thenresult = a;elsif (sel2 = 1) thenresult = b;elseresult = 0;end if;end process;end test1_body;,Wait : I can do the same join with Concurrent Statement,Concurrent Statement并行描述,Process Statement过程描述,Q : What is the different between Concurrent and Process Statement 问:并行和过程描
36、述有什么不同?A : For this simple example, both Concurrent and Process can do the same job. But some function must use Process Statement to do答:对于此例,两种方法可完成同一工作.但是,有些功能必须用过程描述完成.,How to . ? 如何,Now I know what is Sequential Logic butQ : How to implement of Sequential Logic in VHDL?问:在VHDL中如何实现顺序逻辑?Sequentia
37、l Logic can be implemented by Process Statement describe the logic with some CLOCK signal可以用带有时钟信号的过程描述来完成.,Process StatementforSequential Logic,顺序逻辑中的过程描述,How to do the Latch 如何进行锁存,Entity test1 isport (clk, d , reset : in bit; q : out bit);end test1;architecture test1_body of test1 isbeginprocess
38、(clk, d, reset)begin if (reset = 1) then q = 0; elsif (clk = 1) then q = d; end if;end process;end test1_body;,This is a LATCH,If I modify the code to如果修改代码来,Entity test1 isport (clk, d , reset : in bit; q : out bit);end test1;architecture test1_body of test1 isbeginprocess (clk)begin if (reset = 1)
39、 then q = 0; elsif (clk = 1) then q = d; end if;end process;end test1_body;,Note : the result is totally different注意:结果完全不同,What is it ?为什么?,I get a Flip-Flop not a LATCH这是 触发器,不是锁存器,Why I have a Flip-Flop not a Latch为什么成了触发器而不锁存器?,Latch with a Sensitivity list 锁存器的敏感度表如下process (clk, d, reset)Flip-
40、Flop with a Sensitivity list触发器的敏感度表这样process(clk)Q : What is the Sensitivity list use for ?问:什么是适用的敏感度表?A : The OUTPUT change when the Sensitivity list change答:当敏感度表改变时输出也改变.,More Detail更多细节,process (clk, d, reset)this say that the OUTPUT change when either clk, d or reset change, if clk, d or rese
41、t not change, then maintain the outputwhat kind of device will provide this function ?当CLK,D,RESET中任一个改变时,输出也改变. 如果它不改变,则输出不变什么样的设备可提供这种功能?,LATCH锁存器,process (clk)this say that OUTPUT change when CLK change, if clk does not change, maintain the outputwhat kind of device will provide this function ?当C
42、LK改变输出改变,CLK不变时输出不变有这种功能的是什么类型的器件?,Flip-Flop触发器,Now you can see VHDL is very powerful, but if you dont know what you are doing, you may not get what you want现在,你已知道VHDL功能很强,但是如果你不知道你在做什么,还是得不到你想要的东西e.g. you want a latch but actually you get a Flip-Flop比如,你想要一个锁存器,可是实际却得到一个触发器,The other way of coding
43、其他编程方法,LIBRARY IEEE;USE IEEE.std_logic_1164.all;ENTITY tdff ISPORT(clk, d: in std_logic; q : out std_logic);END tdff;ARCHITECTURE behaviour OF tdff ISBEGINPROCESSBEGINwait until clk = 1;q = d;END PROCESS;END behaviour;,Compare IF-THEN-ELSE vs WATI UNTIL 比较IF-THEN-ELSE和WATI UNTIL,LIBRARY IEEE;USE IEE
44、E.std_logic_1164.all;ENTITY tdff ISPORT(clk, d: in std_logic; q : out std_logic);END tdff;architecture behaviour OF tdff ISBEGINPROCESSBEGINwait until clk = 1;q = d;END PROCESS;END behaviour;,Entity test1 isport (clk, d : in bit; q : out bit);end test1;architecture test1_body of test1 isbeginprocess
45、 (clk)begin if (clk = 1) then q = d; end if;end process;end test1_body;,Entity test1 isport (clk, d : in bit; q : out bit);end test1;architecture test1_body of test1 isbeginprocess (clk,d)begin if (clk = 1 and clkevent) then q = d; end if;end process;end test1_body;,They are all the same,DFF,Review,
46、Concurrent Statement for 并行描述combinational logic (without Flip-flop circuit)组合逻辑(非触发器)eg. decoder, multiplixer, multiplier, adder如解码器,多路器,加法器Process Statement for 过程描述combinational logic (without Flip-Flop circuit)组合逻辑Sequential logic (with Flip-Flop circuit)顺序逻辑e.g. State machine, counters, controller如状态机,计数器,控制器,
