1、 PT7313E Stereo Audio Processor for Car AudioDESCRIPTION The PT7313E is an audio processor designed for versatile application, including 3 stereo input selectors with adjustable gain, master volume control with low frequency loudness compensation, individual output attenuator and tone control. It is
2、 a good solution for the car audio signal processing. Due to the high reliability requirement from the car audio business, the PT7313E improves both audio performance and input surge current capability that make PT7313E the best solution for the cost-effective car audio systems. APPLICATIONS Car Aud
3、io Home Audio System Powered Speaker System FEATURES 3 stereo inputs with gain selection, range from 0dB to +11.25dB in 3.75dB/step Master volume from 0 dB to -78.75dB in 1.25dB/step Speaker attenuator for balance and fader, range from 0dB to -38.75dB in 1.25dB/step Each channel output can be muted
4、individually. Low frequency loudness compensation Bass and Treble control, range from -14dB to +14dB in 2dB/step Wide operation range (VDD = 4V to 10V) APPLICATION CIRCUIT 1234567891011121314 1516171819202122232425262728REFVDDAGNDTREB_LTREB_RRINROUTLOUD_RRIN3RIN2RIN1LOUD_LLIN3LIN2 LIN1LINLOUTBOUT_LB
5、IN_LBIN_RBOUT_RRROUTLROUTRFOUTLFOUTDGNDSDASCL2.2uF2.2uF22uFVDD2.7n2.7n100n100n100n100n100n100n5.6K5.6KFront LeftFront RightRear LeftRear Right10uF10uF10uF10uFPowerAmplifier2.2uF2.2uF2.2uF2.2uF2.2uF2.2uFAUDIO 1AUDIO 2AUDIO 32.2K2.2K2.2K2.2K2.2K2.2KLLLRRRInput SurgeProtectionMCUPT2313EPT7313E Princeto
6、n Technology Corp.ANGUS ELECTRONICS CO., LTDTel: (852) 2345 0540 Fax: (852) 2345 9948 Web Site: .hkV1.0 1 February 2010PT7313EV1.0 2 February 2010BLOCK DIAGRAM LOUTLIN1LIN2LIN3REFLOUDNESSLINLOUD_LREFBOUT_LBIN_LTREB_LTREBLEBASSLFOUTLROUTREFREF REFREFLOUDNESSREFTREBLEBASSRROUTRFOUTTREB_RBOUT_RLOUD_RRI
7、NRIN3RIN2RIN1ROUTREFVDDREFAGNDREFSCLSDADGNDI2CDECODERBIASBIN_RSpeaker AttenuatorWith Mute Master VolumeInput SW and GAINInput SW and GAININT RefLoud SWPrinceton Technology Corp.ANGUS ELECTRONICS CO., LTDTel: (852) 2345 0540 Fax: (852) 2345 9948 Web Site: .hkPT7313EV1.0 3 February 2010ORDER INFORMATI
8、ON Valid Part Number Package Type Top Code PT7313E-S 28 Pins, SOP, 300mil PT7313E PIN CONFIGURATION 1234567891011121314 1516171819202122232425262728REFVDDAGNDTREB_LTREB_RRINROUTLOUD_RRIN3RIN2RIN1LOUD_LLIN3LIN2 LIN1LINLOUTBOUT_LBIN_LBIN_RBOUT_RRROUTLROUTRFOUTLFOUTDGNDSDASCLPT7313EPrinceton Technology
9、 Corp.ANGUS ELECTRONICS CO., LTDTel: (852) 2345 0540 Fax: (852) 2345 9948 Web Site: .hkPT7313EV1.0 4 February 2010PIN DESCRIPTION Pin Name I/O Description Pin No. REF - Analog reference voltage (1/2VDD) 1 VDD - Supply input voltage 2 AGND - Analog ground 3 TREB_L I Left channel input for treble cont
10、roller 4 TREB_R I Right channel input for treble controller 5 RIN I Right channel volume controller input 6 ROUT O Right channel Input selector output 7 LOUD_R I Right channel loudness input 8 RIN3 I Right channel input 3 9 RIN2 I Right channel input 2 10 RIN1 I Right channel input 1 11 LOUD_L I Lef
11、t channel loudness input 12 LIN3 I Left channel input 3 13 LIN2 I Left channel input 2 14 LIN1 I Left channel input 1 15 LIN I Left channel volume controller input 16 LOUT O Left channel Input selector output 17 BIN_L I Left channel input for bass controller 18 BOUT_L O Left channel output for bass
12、controller 19 BIN_R I Right channel input for bass controller 20 BOUT_R O Right channel output for bass controller 21 RROUT O Right rear speaker output 22 LROUT O Left rear speaker output 23 RFOUT O Right front speaker output 24 LFOUT O Left front speaker output 25 DGND - Digital ground 26SDA I I2C
13、data input 27 SCL I I2C clock input 28 Princeton Technology Corp.ANGUS ELECTRONICS CO., LTDTel: (852) 2345 0540 Fax: (852) 2345 9948 Web Site: .hkPT7313EV1.0 5 February 2010CONTROL BUS SPECIFICATION BUS INTERFACE All functions of the PT7313E are controlled by the I2C interface, the interface is cons
14、isting by SDA and SCL pins. Detail protocol of the I2C bus will discuss on the next section. It should be noted that the bus level pull-up resistors connected to the PT7313E positive supply voltage may required in some application especially the MCU output high level is no enough. DATA VALIDITY A da
15、ta on the SDA Line is considered valid and stable only when the SCL Signal is in HIGH State. The HIGH and LOW State of the SDA Line can only change when the SCL signal is LOW. Please refer to the figure below. START AND STOP CONDITIONS A Start Condition is activated when 1) The SCL is set to HIGH an
16、d 2) SDA shifts from HIGH to LOW State. The Stop Condition is activated when 1) SCL is set to HIGH and 2) SDA shifts from LOW to HIGH State. Please refer to the timing diagram below BYTE FORMAT Every byte transmitted to the SDA Line consists of 8 bits. Each byte must be followed by an Acknowledge Bi
17、t. The MSB is first transmitted. Princeton Technology Corp.ANGUS ELECTRONICS CO., LTDTel: (852) 2345 0540 Fax: (852) 2345 9948 Web Site: .hkPT7313EV1.0 6 February 2010ACKNOWLEDGE During the Acknowledge clock pulse (ACK), the SDA output port of the master device (P) would be sets on Hi-Z state, if pe
18、ripheral device (ex : audio processor) recognize the I2C command the SDA line will be pull-down by slave device during the SCL clock pulse held in HIGH state period. Please refer to the diagram below. The slave device that has been addressed to generate an Acknowledge after receiving each byte, othe
19、rwise, the SDA Line will remain at the High level in period of the ninth (9th) clock pulse. In this case, the host controller will generate a STOP sign in order to abort the transfer mission. TRANSMISSION WITHOUT ACKNOWLEDGE If the application does not need to verify the Acknowledge signal that gene
20、rated by the slave device is right or not, host controller can just bypass the acknowledge check and transmit next data byte to the slave device. If this approach is used, there are greater chances of faulty operation as well as decrease in noise immunity. INTERFACE PROTOCOL The interface protocol s
21、equence was defined in below section: A Start sign A Chip Address of the desire slave device. The W Bit must be “0” (written). The PT7313E will always response an Acknowledge on the end of each byte. A Data Sequence (N-Bytes + Acknowledge) A Stop Condition PT7313E Address MSB First Byte LSB MSB LSB
22、MSB LSB START 1 0 0 0 1 0 0 W ACK DATA ACK DATA ACK STOP Chip Address Data Transmitting (N-Bytes + Acknowledge) ACK=Acknowledge PT7313E CHIP ADDRESS The PT7313E chip address is 88H AND binary table is shown on below. MSB LSB 1 0 0 0 1 0 0 0 Princeton Technology Corp.ANGUS ELECTRONICS CO., LTDTel: (8
23、52) 2345 0540 Fax: (852) 2345 9948 Web Site: .hkPT7313EV1.0 7 February 2010DATA BYTES MSB LSB Function 0 0 B2 B1 B0 A2 A1 A0 Master Volume 1 1 0 B1 B0 A2 A1 A0 Speaker ATT LR 1 1 1 B1 B0 A2 A1 A0 Speaker ATT RR 1 0 0 B1 B0 A2 A1 A0 Speaker ATT LF 1 0 1 B1 B0 A2 A1 A0 Speaker ATT RF 0 1 0 G1 G0 LD S1
24、 S0 Input Switch and Gain 0 1 1 0 C3 C2 C1 C0 Bass Control 0 1 1 1 C3 C2 C1 C0 Treble Control DATA RATE The PT7313E support Standard-Mode (100kbit/s) I2C data rate In all operation condition, in specified condition it also support Fast-Mode (400kbit/s) I2C data rate, please refer to the follow table
25、: MCU Level PT7313E VDD Voltage 4V 5V 6V 7V 8V 9V 10V 2.5V F F x x x x x 3.3V F F F F S S x 5V x F F F F F F Notes: 1. x = Not allow in this combination; S = Standard Mode Supported, F = Fast Mode Supported. 2. Data rate specification is design guarantee only, not fully tested in every combination.
26、I2C BUS INITIAL TIME The PT7313E is controlled by the I2C bus command; each time the supply voltage applied to chip it needs an initial time to reset all of the internal decoder register, in this period access the I2C bus is prohibited. The initial time is determinate by capacitance it attached on R
27、EF pin (CREF) and Td. For proper operation USER must check the I2C starts timing is fit this requirement and recommended Td timing shown on next page is 50mS. VDDVREFI2C90% VREFI2C PROHIBIT TdPOWER ONI2C STARTS50mSPrinceton Technology Corp.ANGUS ELECTRONICS CO., LTDTel: (852) 2345 0540 Fax: (852) 23
28、45 9948 Web Site: .hkPT7313EV1.0 8 February 2010FUNCTION DESCRIPTION MASTER VOLUME The table below gives a detailed description of the Master Volume Data Bytes. For example, a volume of -37.5dB is given by 0 0 0 1 1 1 1 0. MSB LSB Function 0 0 B2 B1 B0 A2 A1 A0 1.25dB/step 0 0 0 0 0 0 1 -1.25 0 1 0
29、-2.5 0 1 1 -3.75 1 0 0 -5 1 0 1 -6.25 1 1 0 -7.5 1 1 1 -8.75 0 0 B2 B1 B0 A2 A1 A0 10dB/step 0 0 0 0 0 0 1 -10 0 1 0 -20 0 1 1 -30 1 0 0 -40 1 0 1 -50 1 1 0 -60 1 1 1 -70 SPEAKER ATTENUATORS The speaker attenuator in most of car audio system is performs balance and fader function, the table below gi
30、ves a detailed description of the speaker attenuators data bytes. Total control range of the speaker attenuator is from 0dB to -37.5dB. Example 1, an attenuation gain of -6.25dB on the Speaker Right Rear channel is combined 0dB and -6.25dB, therefore it should be given by: 1 1 1 0 0 1 0 1. Example 2
31、, an attenuation gain of -32.5dB on the Speaker Left Front channel is combined -30dB and -2.5dB, therefore it should be given by: 1 0 0 1 1 0 1 0. MSB LSB Function 1 0 0 B1 B0 A2 A1 A0 Speaker LF 1 0 1 B1 B0 A2 A1 A0 Speaker RF 1 1 0 B1 B0 A2 A1 A0 Speaker LR 1 1 1 B1 B0 A2 A1 A0 Speaker RR 0 0 0 0
32、0 0 1 -1.25 0 1 0 -2.50 1 1 -3.75 1 0 0 -51 0 1 -6.25 1 1 0 -7.51 1 1 -8.75 0 0 0 0 1 -10 1 0 -201 1 -30 1 1 1 1 1 Mute Princeton Technology Corp.ANGUS ELECTRONICS CO., LTDTel: (852) 2345 0540 Fax: (852) 2345 9948 Web Site: .hkPT7313EV1.0 9 February 2010INPUT SELECTOR The PT7313E provides 3 stereo i
33、nput selector and following table shows the definition of the correspond register. The LD register is determinate the loudness function is ON or OFF, and G0 and G1 determinate the input gain of the selector output, this function is use to matching level of different sources to avoid overall volume d
34、ifference. MSB LSB Function 0 1 0 G1 G0 LD S1 S0 Audio switch 0 0 Stereo 10 1 Stereo 2 1 0 Stereo 30 Loudness ON 1 Loudness OFF 0 0 +11.25dB 0 1 +7.5dB1 0 +3.75dB 1 1 0dB BASS AND TREBLE DATA BYTES The following table shows a detailed description of the Bass and Treble Data Byte. For example a Trebl
35、e at -12dB is given by: 0 1 1 1 0 0 0 1 (0x71). MSB LSB Function 0 1 1 0 C3 C2 C1 C0 Bass 0 1 1 1 C3 C2 C1 C0 Treble 0 0 0 0 -14dB0 0 0 1 -12dB 0 0 1 0 -10dB0 0 1 1 -8dB 0 1 0 0 -6 dB0 1 0 1 -4 dB 0 1 1 0 -2 dB0 1 1 1 0 dB 1 1 1 1 0 dB 1 1 1 0 +2 dB 1 1 0 1 +4 dB1 1 0 0 +6 dB 1 0 1 1 +8 dB1 0 1 0 +1
36、0 dB 1 0 0 1 +12 dB1 0 0 0 +14 dB Princeton Technology Corp.ANGUS ELECTRONICS CO., LTDTel: (852) 2345 0540 Fax: (852) 2345 9948 Web Site: .hkPT7313EV1.0 10 February 2010TUNNING TONE CURVE CHARACTERISTICS The tone control response character is possible tuned to match users wishes, please refer to fol
37、lowing chart to realize the characteristics between the different component values. For the reasons to achieve low distortion and precision response gain, using high quality low tolerance X7R SMD capacitor on tone circuit is recommended. The loudness boost gain is adaptive with the master volume att
38、enuation setting, more attenuation means more low frequency boost, in the maximum volume the loudness boost will return to flat response. -6+16-4-2+0+2+4+6+8+10+12+14dBgA10 20k20 50 100 200 500 1k 2k 5kHz-6+16-4-2+0+2+4+6+8+10+12+14dBgA10 50k20 50 100 200 500 1k 2k 5k 10k 20kHzPT7313E Bass Response
39、VS CAP PT7313E Treble Response VS CAP -50-10-45-40-35-30-25-20-15dBV10 20k20 50 100 200 500 1k 2k 5kHz-80+0-70-60-50-40-30-20-10dBgA20 20k50 100 200 500 1k 2k 5k 10kHzPT7313E Loudness Response VS CAP (VOLUME=-40dB) PT7313E Loudness Response VS Master Volume 2.7nF 1.5nF 1nF 68nF 150nF100nF 56nF 100nF
40、220nFOPENPrinceton Technology Corp.ANGUS ELECTRONICS CO., LTDTel: (852) 2345 0540 Fax: (852) 2345 9948 Web Site: .hkPT7313EV1.0 11 February 2010ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min. Max. Unit Operating supply voltage VDD - 10 V Latch up current Iin -100 +100 mA ESD grade Human body model HB
41、M -2 +2 KV Machine model MM -0.2 +0.2 KV Input voltage Vin -0.3 VDD+0.3 V Operating temperature Topr -40 +85 Storage temperature Tstg -65 +150 QUICK REFERENCE DATA Parameter Symbol Min. Typ. Max. Unit Supply voltage VDD 4 9 10 V Max. input signal handling VCL 2.3 2.6 - Vrms Total harmonic distortion
42、 (1Vrms,1KHz) THD - 0.03 0.07 % Signal To noise ratio S/N - 100 - dBV Channel separation (f=1KHz) Sc - 100 - dB Volume control 1.25dB step - -78.75 - 0 dB Bass THD=1% 2.3 2.6 - VrmsInput separation ISINF=20 20KHz 90 100 - dB Min. input gain GINmin- -1 0 1 Max. input gain GINmax10.5 11.25 12 dB Step
43、resolution GINst- 3.75 - Gain set error EA- -1 0 1 dB Minimum load RL Vo=2Vrms, LOUT, ROUT 5 - - K DC offset VDCO0dB to +11.25dB - 3 10 mV Volume Control Input resistance RINVOL=0dB 13 20 27 K Min. attenuation AVMIN- -1 0 1 dB Max. attenuation AVMAX-75 -78.75 -82 Step resolution ASTEP1.15 1.25 1.3 d
44、B Attenuation set error EAVOL=0 -70dB -1 0 1 dB Speaker Attenuators Max. Gain AVMIN- -1 0 +1 dB Max. attenuation AVMAX-36 -37.5 -39 Step resolution SSTEP1.15 1.25 1.35 dB Attenuation set error EA- -1 0 1 Output mute attenuation AMUTE- 100 - dB DC offset VDCO0dB to MUTE - 5 10 mV Bass Control Control
45、 range Gb Max. Boost/Cut 12 14 16 dB Step resolution BSTEP- 1.7 2 2.3 dB Feedback resistance RB34 44 58 K Treble Control Control range Gt Max. Boost/Cut 12 14 16 dB Step resolution TSTEP- 1.7 2 2.3 dB Loudness Control Boost gain GLDVolume=-40dB, F=20Hz 18 20 22 dB Audio Outputs Max. output level VOM
46、AXTHD=1% 2.3 2.6 - VrmsDC voltage level VOUT- 0.49 0.5 0.51 VDD Minimum load RL - 5 - - K General Signal to noise ratio SNR All Gain=0dB, A-weighted - 100 - dBV All Gains=0dB, Muted - 100 - Distortion THDAll Gain=0, Vin=1Vrms - 0.03 0.07 % All Gain=0, Vin=100Vrms - 0.01 0.03 Channel separation Cs L
47、to R or R to L channel 90 100 - dB I2C crosstalk Ct I2C to audio output - 90 - dB Ripple rejection PSRR CREF=22F, F=100Hz - 75 - dB I2C Bus Input low voltage VILVDD=9V - - 1 V Input high voltage VIHVDD=9V 3 - Input current IIN- -5 - +5 A SDA pull down voltage Vack Rpull up=3K, ACK=active - 0.4 - V P
48、rinceton Technology Corp.ANGUS ELECTRONICS CO., LTDTel: (852) 2345 0540 Fax: (852) 2345 9948 Web Site: .hkPT7313EV1.0 13 February 2010-16+16-12-8-4+0+4+8+12dBgA20 30k50 100 200 500 1k 2k 5k 10kHz-16+16-12-8-4+0+4+8+12dBgA20 30k50 100 200 500 1k 2k 5k 10kHzBass Response Treble Response -130-70-120-11
49、0-100-90-80dB20 30k50 100 200 500 1k 2k 5k 10kHz-120-20-100-80-60-40dBrA20 20k50 100 200 500 1k 2k 5kHz2 Channel Crosstalk PSRR 0.003200.010.020.050.10.20.512510%1m 42m 5m 10m 20m 50m 200m 500m 1 2V-110-50-100-90-80-70-60dBV20 20k50 100 200 500 1k 2k 5kHzOutput THD VS VDD Voltage Input Selector Separation 4V 5V 8V 9V 10V (R
