1、Recognized as an IEEE P1364.1-2001American National Standard June 15, 2001The Institute of Electrical and Electronics Engineers, Inc.345 East 47th Street, New York, NY 10017-2394, USACopyright 2001 by the Institute of Electrical and Electronics Engineers, Inc.All rights reserved. Published 2001. Pri
2、nted in the United States of AmericaISBN XXXXXXXXXXNo part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the priorwritten permission of the publisher.IEEE P1364.1 / D1.6Draft Standard for Verilog RegisterTransfer Level SynthesisPrepared by
3、 the Verilog Synthesis Interoperability Working Group of theDesign Automation Standards CommitteeSponsorDesign Automation Standards Committeeof the IEEE Computer SocietyIEEE Standards documents are developed within the Technical Committees of the IEEE Societies and theStandards Coordinating Committe
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14、 subject matter covered by patent rights. By publication of this standard,no position is taken with respect to the existence or validity of any patent rights inconnection therewith. The IEEE shall not be responsible for identifying all patentsfor which a license may be required by an IEEE standard o
15、r for conducting inquiriesinto the legal validity or scope of those patents that are brought to its attention.ii Copyright 2001 IEEE. All rights reserved.This is an unapproved IEEE Standards Draft, subject to change.Introduction(This introduction is not a part of IEEE P1364.1, Draft Standard Registe
16、r Transfer Level Subset Based on the VerilogHardware Description Language.)This standard describes a standard syntax and semantics for Verilog HDL based RTL synthesis. It defines thesubset of IEEE 1364-2001 (Verilog HDL) that is suitable for RTL synthesis and defines the semantics ofthat subset for
17、the synthesis domain.The purpose of this standard is to define a syntax and semantics that can be used in common by all compliantRTL synthesis tools to achieve uniformity of results in a similar manner to which simulation and analysistools use the IEEE 1364 standard. This will allow users of synthes
18、is tools to produce well defined designswhose functional characteristics are independent of a particular synthesis implementation by making theirdesigns compliant with this standard.The standard is intended for use by logic designers and electronic engineers.Initial work on this standard started as
19、a RTL synthesis subset working group under Open Verilog Interna-tional (OVI). After OVI approved of the draft 1.0 with an overwhelming affirmative response, an IEEE PARwas obtained to clear its way for IEEE standardization. Most of the members of the original group continuedto be part of the Pilot G
20、roup under P1364.1 to lead the technical work. The active members at the time ofOVI draft 1.0 publication were as follows:Victor BermanJ. Bhasker (Chair)David BishopVassilios GerousisDon HejnaMike QuayleAmbar SarkarDoug SmithYatin TrivediRohit VoraThe Draft Std 1364.1 working group organizationMany
21、individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the IEEE P1364.1 working group is located in the United States.The members of the IEEE P1364.1 working group had voting privileges, and all motions had to be approvedby t
22、his group to be implemented. All task forces and subgroups focused on some specific areas, and theirrecommendations were eventually voted on by the IEEE P1364.1 working group.Verilog is a registered trademark of Cadence Design Systems, Inc.Copyright 2001 IEEE. All rights reserved. iiiThis is an unap
23、proved IEEE Standards Draft, subject to change.iv Copyright 2001 IEEE. All rights reserved.This is an unapproved IEEE Standards Draft, subject to change.IEEE P1364.1REGISTER TRANSFER LEVEL SYNTHESIS June 15, 2001ContentsSection 1 Overview 71.1 Scope 71.2 Compliance to this standard. 71.3 Terminology
24、. 71.4 Conventions . 81.5 Contents of this standard 81.6 Examples 9Section 3 Definitions 9Section 4 Verification Methodology 104.1 Combinational Logic Verification . 114.2 Sequential Logic Verification 11Section 5 Modeling hardware elements . 125.1 Modeling combinational logic . 125.2 Modeling edge-
25、sensitive sequential logic 135.3 Modeling level-sensitive storage devices 165.4 Modeling three-state drivers 165.5 Support for values x and z 17Section 6 Pragmas 186.1 Conditional compilation metacomments . 186.2 Case decoding attributes 18Section 7 Syntax. 197.1 Lexical conventions . 197.2 Data typ
26、es. 257.3 Expressions 307.4 Assignments . 327.5 Gate and switch level modeling . 347.6 User-defined primitives (UDPs) 377.7 Behavioral modeling 377.8 Tasks and functions 437.9 Disabling of named blocks and tasks. 467.10 Hierarchical structures . 467.11 Configuring the contents of a design . 527.12 S
27、pecify blocks 547.13 Timing checks 547.14 Backannotation using the Standard Delay Format. 547.15 System tasks and functions 547.16 Value change dump (VCD) files 547.17 Compiler directives 547.18 PLI 55Annex A . Syntax summary . 56Copyright 2001 IEEE. All rights reserved. vThis is an unapproved IEEE
28、Standards Draft, subject to change.IEEE P1364.1June 15, 2001 DRAFT STANDARD FOR VERILOGAnnex B . Functional Mismatches 84vi Copyright 2001 IEEE. All right reserved.This is an unapproved IEEE Standards Draft, subject to change.Section 1Overview1.1 ScopeThis standard defines a set of modeling rules fo
29、r writing Verilog HDL descriptions. Adherence to these rules guaran-tee the interoperability of Verilog HDL descriptions between register-transfer level synthesis tools that comply to thisstandard. The standard defines how the semantics of Verilog HDL is used, for example, to describe level- and edg
30、e-sensitive logic. It also describes the syntax of the language with reference to what shall be supported and what shallnot be supported for interoperability.Use of this standard will enhance the portability of Verilog HDL based designs across synthesis tools conforming tothis standard. In addition,
31、 it will minimize the potential for functional mismatch that may occur between the RTLmodel and the synthesized netlist.1.2 Compliance to this standard1.2.1 Model complianceA Verilog HDL model shall be considered compliant to this standard if the model:a) uses only constructs described as supported
32、or ignored in this standard, andb) adheres to the semantics defined in this standard.1.2.2 Tool complianceA synthesis tool shall be considered compliant to this standard if it:a) accepts all models that adhere to the model compliance definition in section 1.2.1.b) supports all pragmas defined in sec
33、tion 6c) produces a netlist model that has the same functionality as the input model based on the conformance rules ofsection 4.Note: A compliant synthesis tool may have more features than those required by this standard. A synthesis tool mayintroduce additional guidelines for writing Verilog HDL mo
34、dels that may produce more efficient logic, or othermechanisms for controlling how a particular description is best mapped to a particular library.1.3 TerminologyThe word shall indicates mandatory requirements strictly to be followed in order to conform to the standard and fromwhich no deviation is
35、permitted (shall equals is required to). The word should is used to indicate that a certain courseof action is preferred but not necessarily required; or that (in the negative form) a certain course of action is depre-Section 1 Copyright 2001 IEEE. All rights reserved 7This is an unapproved IEEE Sta
36、ndards Draft, subject to change.cated but not prohibited (should equals is recommended that). The word may indicates a course of action permissiblewithin the limits of the standard (may equals is permitted).1IEEE P1364.1June 15, 2001 DRAFT STANDARD FOR VERILOGA synthesis tool is said to accept a Ver
37、ilog construct if it allows that construct to be legal input. The construct is saidto interpret the construct (or to provide an interpretation of the construct) by producing logic that represents the con-struct. A synthesis tool shall not be required to provide an interpretation for every construct
38、that it accepts, but onlyfor those for which an interpretation is specified by this standard.The Verilog HDL constructs in this standard are categorized as:Supported RTL synthesis shall interpret a construct, that is, map the construct to hardware.Ignored RTL synthesis shall ignore the construct and
39、 shall not map that construct to hardware.Encountering the construct shall not cause synthesis to fail, but may cause a functionalmismatch between the RTL model and the synthesized netlist. The mechanism, if any, bywhich a RTL synthesis notifies the user of such constructs is not defined. It is acce
40、ptablefor a not supported construct to be part of an ignored construct.Not supported RTL synthesis shall not support the construct. RTL synthesis does not expect to encounterthe construct and the failure mode shall be undefined.1.4 ConventionsThis standard uses the following conventions:a) The body
41、of the text of this standard uses boldface font to denote Verilog reserved words (such as if) andUPPER CASE letters to denote all other Verilog identifiers (such as SHIFTREG_A or N$657).b) The text of the Verilog examples and code fragments is represented in a fixed-width font.c) Syntax text that is
42、 struck-through refers to syntax that is not supported.d) Syntax text that is underlined refers to syntax that is ignored.e) “” are used to represent text in one of several different, but specific forms.f) Any paragraph starting with “Note -” is informative and not part of the standard.1.5 Contents
43、of this standardA synopsis of the sections and annexes is presented as a quick reference. There are seven sections and two annexes.All the sections are the normative parts of this standard, while all the annexes are the informative part of the standard.1) OverviewThis section discusses the conventio
44、ns used in this standard and its contents.2) ReferencesThis section contains bibliographic entries pertaining to this standard.3) DefinitionsThis section defines various terms used in this standard.4) Verification methodologyThis section describes the guidelines for ensuring functtionality matches b
45、efore and after synthesis.5) Modeling hardware elementsThis section defines the styles for inferring special hardware elements.6) PragmasThis section defines the pragmas that are part of this RTL synthesis subset.1The wording of this paragraph is adapted from the IEEE Standards Style Manual, The Ins
46、titute of Electrical and Electronics Engi-neers, Inc., New York, NY, c. 1992.8 Copyright 2001 IEEE. All rights reserved. Section 1This is an unapproved IEEE Standards Draft, subject to change.IEEE P1364.1REGISTER TRANSFER LEVEL SYNTHESIS June 15, 20017) SyntaxThis section describes the syntax of Ver
47、ilog HDL supported for RTL synthesis.8) Annex A: Syntax summaryProvides a summary of the syntax supported for synthesis.9) Annex B: Functional mismatchesThis informative annex describes some cases where a potential exists for functional mismatch to occurbetween the RTL model and the synthesized netl
48、ist.1.6 ExamplesAll examples that appear in this document under “Example:“, are for the sole purpose of demonstrating the syntaxand semantics of Verilog HDL for synthesis. It is not the intent of this clause to demonstrate, recommend, or empha-size coding styles that are more (or less efficient) in
49、generating synthesizable hardware. In addition, it is not the intentof this standard to present examples that represent a compliance test suite, or a performance benchmark, even thoughthese examples are compliant to this standard.Section 2ReferencesThis standard shall be used in conjunction with the following publications. When the following standards are super-seded by an approved revision, the revision shall apply.IEEE Std 1364-2001, IEEE Standard Verilog Language Reference Manual.Section 3DefinitionsThis section defines various terms used in this standard. Terms used wi
