课设报告 数据结构.doc

1、计算机与科学技术专业计算机组成原理与汇编实验实 验 报 告学生姓名： 王明颖 学 号： 14570131 同组成员： 张伟宸 翟芸婷 完成日期： 2016.7.8 成 绩： 2计算机与科学技术专业目录一、实验一1二、实验二13三、实验三18四、实验四31五、心得与体会39六、参考资料39一实验一16位并行进位运算器功能部件的设计与实现（一）总体设计1.1.1问题分析了解并行进位运算器的工作原理和过程，利用多个芯片采用扩展的方式设计出16位并行进位运算器功能部件，并封装调试。1、分析并设计16位并行进位运算器的基本结构；2、选择芯片及若干元器件进行物理连接，完成16位并行进位运算器功能部件的设计

2、，并实现部件的封装；3、对设计出的16位并行进位运算器功能部件进行测试，检查运算器功能部件是否能够正确完成数值运算的功能。运算器（ALU）功能部件是为了完成计算机主机系统设计实践的算术/逻辑运算功能而设计的功能部件，是计算机进行算术/逻辑运算的核心部件。在本范例中设计的运算器功能部件可以对 8 位数据进行算术/逻辑运算。此部件采用了两片 4 位片的 74181，通过串行进位而扩展成 8 位运算器。暂存器(74273)对从总线上面传来的数据进行寄存，可以起到暂存数据的作用。三态门(74244)由控制信号 ALU-BUS 控制，保证 ALU 运算所得到的结果在需要时送上总线，完成算术逻辑运算。1.

3、1.2总体方案设计。 1、设计出部件的逻辑原理图，画出部件的逻辑电路布线图；2、拟定测试数据及测试方法；3、检测模拟仿真测试结果的正确性；4、对设计出的部件进行封装，并写出封装后芯片的功能表。（二）详细设计1.2.1每个模块的功能完成运算1.2.2入出信息输入信息 输出信息 1.2.3处理逻辑1.2.4屏幕显示布局设计图74181功能表74182功能表运算器封装布局设计图（3） 程序编码。- Copyright (C) 1991-2008 Altera Corporation- Your use of Altera Corporations design tools, logic functi

4、ons - and other software and tools, and its AMPP partner logic - functions, and any output files from any of the foregoing - (including device programming or simulation files), and any - associated documentation or information are expressly subject - to the terms and conditions of the Altera Program

5、 License - Subscription Agreement, Altera MegaCore Function License - Agreement, or other applicable license agreement, including, - without limitation, that your use is for the sole purpose of - programming logic devices manufactured by Altera and sold by - Altera or its authorized distributors. Pl

6、ease refer to the - applicable agreement for further details.- PROGRAM Quartus II 64-Bit- VERSION Version 8.0 Build 215 05/29/2008 SJ Full VersionLIBRARY ieee;USE ieee.std_logic_1164.all; LIBRARY work;ENTITY Block1 IS port(cn : IN STD_LOGIC;m : IN STD_LOGIC;a : IN STD_LOGIC_VECTOR(15 downto 0);b : I

7、N STD_LOGIC_VECTOR(15 downto 0);s : IN STD_LOGIC_VECTOR(3 downto 0);f : OUT STD_LOGIC_VECTOR(15 downto 0);END Block1;ARCHITECTURE bdf_type OF Block1 ISattribute black_box : boolean;attribute noopt : boolean;component 74181_0PORT(B0N : IN STD_LOGIC; A0N : IN STD_LOGIC; A1N : IN STD_LOGIC; B1N : IN ST

8、D_LOGIC; A3N : IN STD_LOGIC; B2N : IN STD_LOGIC; A2N : IN STD_LOGIC; M : IN STD_LOGIC; CN : IN STD_LOGIC; B3N : IN STD_LOGIC; S2 : IN STD_LOGIC; S1 : IN STD_LOGIC; S0 : IN STD_LOGIC; S3 : IN STD_LOGIC; PN : OUT STD_LOGIC; GN : OUT STD_LOGIC; F3N : OUT STD_LOGIC; F1N : OUT STD_LOGIC; F0N : OUT STD_LO

9、GIC; F2N : OUT STD_LOGIC);end component;attribute black_box of 74181_0: component is true;attribute noopt of 74181_0: component is true;component 74181_1PORT(B0N : IN STD_LOGIC; A0N : IN STD_LOGIC; A1N : IN STD_LOGIC; B1N : IN STD_LOGIC; A3N : IN STD_LOGIC; B2N : IN STD_LOGIC; A2N : IN STD_LOGIC; M

10、: IN STD_LOGIC; CN : IN STD_LOGIC; B3N : IN STD_LOGIC; S2 : IN STD_LOGIC; S1 : IN STD_LOGIC; S0 : IN STD_LOGIC; S3 : IN STD_LOGIC; PN : OUT STD_LOGIC; GN : OUT STD_LOGIC; F3N : OUT STD_LOGIC; F1N : OUT STD_LOGIC; F0N : OUT STD_LOGIC; F2N : OUT STD_LOGIC);end component;attribute black_box of 74181_1:

11、 component is true;attribute noopt of 74181_1: component is true;component 74181_2PORT(B0N : IN STD_LOGIC; A0N : IN STD_LOGIC; A1N : IN STD_LOGIC; B1N : IN STD_LOGIC; A3N : IN STD_LOGIC; B2N : IN STD_LOGIC; A2N : IN STD_LOGIC; M : IN STD_LOGIC; CN : IN STD_LOGIC; B3N : IN STD_LOGIC; S2 : IN STD_LOGI

12、C; S1 : IN STD_LOGIC; S0 : IN STD_LOGIC; S3 : IN STD_LOGIC; PN : OUT STD_LOGIC; GN : OUT STD_LOGIC; F3N : OUT STD_LOGIC; F1N : OUT STD_LOGIC; F0N : OUT STD_LOGIC; F2N : OUT STD_LOGIC);end component;attribute black_box of 74181_2: component is true;attribute noopt of 74181_2: component is true;compon

13、ent 74181_3PORT(B0N : IN STD_LOGIC; A0N : IN STD_LOGIC; A1N : IN STD_LOGIC; B1N : IN STD_LOGIC; A3N : IN STD_LOGIC; B2N : IN STD_LOGIC; A2N : IN STD_LOGIC; M : IN STD_LOGIC; CN : IN STD_LOGIC; B3N : IN STD_LOGIC; S2 : IN STD_LOGIC; S1 : IN STD_LOGIC; S0 : IN STD_LOGIC; S3 : IN STD_LOGIC; PN : OUT ST

14、D_LOGIC; GN : OUT STD_LOGIC; F3N : OUT STD_LOGIC; F1N : OUT STD_LOGIC; F0N : OUT STD_LOGIC; F2N : OUT STD_LOGIC);end component;attribute black_box of 74181_3: component is true;attribute noopt of 74181_3: component is true;component 74182_4PORT(PN2 : IN STD_LOGIC; GN2 : IN STD_LOGIC; GN3 : IN STD_LO

15、GIC; PN3 : IN STD_LOGIC; CI : IN STD_LOGIC; PN1 : IN STD_LOGIC; PN0 : IN STD_LOGIC; GN1 : IN STD_LOGIC; GN0 : IN STD_LOGIC; CY : OUT STD_LOGIC; CX : OUT STD_LOGIC; CZ : OUT STD_LOGIC);end component;attribute black_box of 74182_4: component is true;attribute noopt of 74182_4: component is true;signal

16、f_ALTERA_SYNTHESIZED : STD_LOGIC_VECTOR(15 downto 0);signalSYNTHESIZED_WIRE_0 : STD_LOGIC;signalSYNTHESIZED_WIRE_1 : STD_LOGIC;signalSYNTHESIZED_WIRE_2 : STD_LOGIC;signalSYNTHESIZED_WIRE_3 : STD_LOGIC;signalSYNTHESIZED_WIRE_4 : STD_LOGIC;signalSYNTHESIZED_WIRE_5 : STD_LOGIC;signalSYNTHESIZED_WIRE_6

17、: STD_LOGIC;signalSYNTHESIZED_WIRE_7 : STD_LOGIC;signalSYNTHESIZED_WIRE_8 : STD_LOGIC;signalSYNTHESIZED_WIRE_9 : STD_LOGIC;signalSYNTHESIZED_WIRE_10 : STD_LOGIC;BEGIN b2v_inst : 74181_0PORT MAP(B0N = b(0), A0N = a(0), A1N = a(1), B1N = b(1), A3N = a(3), B2N = b(2), A2N = a(2), M = m, CN = cn, B3N =

18、b(3), S2 = s(2), S1 = s(1), S0 = s(0), S3 = s(3), PN = SYNTHESIZED_WIRE_6, GN = SYNTHESIZED_WIRE_5, F3N = f_ALTERA_SYNTHESIZED(3), F1N = f_ALTERA_SYNTHESIZED(1), F0N = f_ALTERA_SYNTHESIZED(0), F2N = f_ALTERA_SYNTHESIZED(2);b2v_inst1 : 74181_1PORT MAP(B0N = b(4), A0N = a(4), A1N = a(5), B1N = b(5), A

19、3N = a(7), B2N = b(6), A2N = a(6), M = m, CN = SYNTHESIZED_WIRE_0, B3N = b(7), S2 = s(2), S1 = s(1), S0 = s(0), S3 = s(3), PN = SYNTHESIZED_WIRE_3, GN = SYNTHESIZED_WIRE_4, F3N = f_ALTERA_SYNTHESIZED(7), F1N = f_ALTERA_SYNTHESIZED(5), F0N = f_ALTERA_SYNTHESIZED(4), F2N = f_ALTERA_SYNTHESIZED(6);b2v_

20、inst2 : 74181_2PORT MAP(B0N = b(8), A0N = a(8), A1N = a(9), B1N = b(9), A3N = a(11), B2N = b(10), A2N = a(10), M = m, CN = SYNTHESIZED_WIRE_1, B3N = b(11), S2 = s(2), S1 = s(1), S0 = s(0), S3 = s(3), PN = SYNTHESIZED_WIRE_7, GN = SYNTHESIZED_WIRE_9, F3N = f_ALTERA_SYNTHESIZED(11), F1N = f_ALTERA_SYN

21、THESIZED(9), F0N = f_ALTERA_SYNTHESIZED(8), F2N = f_ALTERA_SYNTHESIZED(10);b2v_inst3 : 74181_3PORT MAP(B0N = b(12), A0N = a(12), A1N = a(13), B1N = b(13), A3N = a(15), B2N = b(14), A2N = a(14), M = m, CN = SYNTHESIZED_WIRE_2, B3N = b(15), S2 = s(2), S1 = s(1), S0 = s(0), S3 = s(3), PN = SYNTHESIZED_

22、WIRE_8, GN = SYNTHESIZED_WIRE_10, F3N = f_ALTERA_SYNTHESIZED(15), F1N = f_ALTERA_SYNTHESIZED(13), F0N = f_ALTERA_SYNTHESIZED(12), F2N = f_ALTERA_SYNTHESIZED(14);b2v_inst4 : 74182_4PORT MAP(PN2 = SYNTHESIZED_WIRE_3, GN2 = SYNTHESIZED_WIRE_4, GN3 = SYNTHESIZED_WIRE_5, PN3 = SYNTHESIZED_WIRE_6, CI = cn

23、, PN1 = SYNTHESIZED_WIRE_7, PN0 = SYNTHESIZED_WIRE_8, GN1 = SYNTHESIZED_WIRE_9, GN0 = SYNTHESIZED_WIRE_10, CY = SYNTHESIZED_WIRE_1, CX = SYNTHESIZED_WIRE_2, CZ = SYNTHESIZED_WIRE_0);f = f_ALTERA_SYNTHESIZED;END; （四）遇到的问题及解决方法分析遇到的问题：进位怎样传入。解决办法：通过74182芯片来传输进位。（五）尚未解决的问题及其应对策略尚未解决的问题：运算结果总比实际结果多一应对策略

24、：S0S3的赋值不同所运行的运算不同，可以通过改变S0S3的赋值来解决。二实验二带字位扩展存储器功能部件的设计与实现（一）总体设计2.1.1问题分析了解随机存储器的工作原理和过程，熟悉随机存储器的读写原理。根据存储器的工作原理，并且按照存储器字位扩展的基本原则完成存储器功能部件的设计，并实现器件封装，测试存储器的读写功能。1、设计出存储器功能部件的基本结构；2、选择芯片及若干元器件进行物理连接，完成存储器部件的设计并实现部件的封装；3、对该部件进行模拟仿真测试，检查存储器功能部件的数据读写是否正确。功能介绍： 存储器功能部件（Memory）是为了提供存储数据和程序而设计的功能部件。可作为主机系

25、统的主存储器使用。 在存储器功能部件中，设计了主存地址寄存器（MAR）和主存数据寄存器（MDR），作为主存与 CPU 进行数据交换的接口。MAR 接收、暂存总线上的主存地址，MDR 暂存输出到总线上的数据。 CPMAR 和 CPMDR 管脚分别作为主存地址寄存器（MAR）和主存数据寄存器（MDR）的数据接收控制信号。RD 作为存储器的读控制信号（上升沿触发），在 RD 为高电位 (即：存储器数据输出有效) 期间，应发出 CPMDR 脉冲控制信号，使存储器的读出数据锁存到存储器数据寄存器 MDR 中。WR 和 WRE 分别作为存储器的写控制信号和写使能控制信号，在 WRE为高电位期间，发出 WR

26、 脉冲控制信号（上升沿有效），则可以把输入数据写入到主存储器中。RAM-BUS 控制信号（低电位有效）完成将存储器的输出数据通过三态门输出的功能。2.1.2总体方案设计。 1、设计出部件的逻辑原理图，画出部件的逻辑电路布线图；2、拟定测试数据及测试方法；3、检测模拟仿真测试结果的正确性；4、对设计出的部件进行封装，并写出封装后芯片的功能表。（二）详细设计2.2.1每个模块的功能具有扩展功能的存储器 存储功能2.2.2处理逻辑 2.2.3屏幕显示布局设计图74273功能表74244功能表存储器封装布局设计图（3） 程序编码。/ Copyright (C) 1991-2008 Altera Cor

27、poration/ Your use of Altera Corporations design tools, logic functions / and other software and tools, and its AMPP partner logic / functions, and any output files from any of the foregoing / (including device programming or simulation files), and any / associated documentation or information are e

28、xpressly subject / to the terms and conditions of the Altera Program License / Subscription Agreement, Altera MegaCore Function License / Agreement, or other applicable license agreement, including, / without limitation, that your use is for the sole purpose of / programming logic devices manufactur

29、ed by Altera and sold by / Altera or its authorized distributors. Please refer to the / applicable agreement for further details./ PROGRAM Quartus II 64-Bit/ VERSION Version 8.0 Build 215 05/29/2008 SJ Full Versionmodule Block12(WRE,WR,RD,clka,clkd,CLRN,GN,a,in,out);inputWRE;inputWR;inputRD;inputclk

30、a;inputclkd;inputCLRN;inputGN;input15:0 a;input15:0 in;output15:0 out;wire15:0 b;wire7:0 c;wire15:0 out_ALTERA_SYNTHESIZED;wire15:0 q;74273 b2v_inst(.D2(a1),.D3(a2),.D1(a0),.D4(a3),.D7(a6),.D6(a5),.D5(a4),.D8(a7),.CLK(clka),.CLRN(CLRN),.Q4(c3),.Q1(c0),.Q2(c1),.Q3(c2),.Q6(c5),.Q5(c4),.Q7(c6),.Q8(c7);

31、74273 b2v_inst1(.D2(in1),.D3(in2),.D1(in0),.D4(in3),.D7(in6),.D6(in5),.D5(in4),.D8(in7),.CLK(clkd),.CLRN(CLRN),.Q4(b3),.Q1(b0),.Q2(b1),.Q3(b2),.Q6(b5),.Q5(b4),.Q7(b6),.Q8(b7);74273 b2v_inst2(.D2(in9),.D3(in10),.D1(in8),.D4(in11),.D7(in14),.D6(in13),.D5(in12),.D8(in15),.CLK(clkd),.CLRN(CLRN),.Q4(b11)

32、,.Q1(b8),.Q2(b9),.Q3(b10),.Q6(b13),.Q5(b12),.Q7(b14),.Q8(b15);74244 b2v_inst3(.1A2(q1),.1A4(q3),.1A1(q0),.1A3(q2),.1GN(GN),.2A3(q6),.2GN(GN),.2A1(q4),.2A4(q7),.2A2(q5),.1Y2(out_ALTERA_SYNTHESIZED1),.1Y4(out_ALTERA_SYNTHESIZED3),.2Y1(out_ALTERA_SYNTHESIZED4),.1Y1(out_ALTERA_SYNTHESIZED0),.2Y3(out_ALT

33、ERA_SYNTHESIZED6),.2Y4(out_ALTERA_SYNTHESIZED7),.1Y3(out_ALTERA_SYNTHESIZED2),.2Y2(out_ALTERA_SYNTHESIZED5);74244 b2v_inst4(.1A2(q9),.1A4(q11),.1A1(q8),.1A3(q10),.1GN(GN),.2A3(q14),.2GN(GN),.2A1(q12),.2A4(q15),.2A2(q13),.1Y2(out_ALTERA_SYNTHESIZED9),.1Y4(out_ALTERA_SYNTHESIZED11),.2Y1(out_ALTERA_SYN

34、THESIZED12),.1Y1(out_ALTERA_SYNTHESIZED8),.2Y3(out_ALTERA_SYNTHESIZED14),.2Y4(out_ALTERA_SYNTHESIZED15),.1Y3(out_ALTERA_SYNTHESIZED10),.2Y2(out_ALTERA_SYNTHESIZED13);lpm_ram_dq0b2v_inst5(.we(WRE),.inclock(WR),.outclock(RD),.address(c),.data(b),.q(q);assignout = out_ALTERA_SYNTHESIZED;endmodule（四）遇到的

35、问题及解决方法分析遇到的问题：标注的时候要注意不要在线上空白处直接直接，不然程序不认，产生很多错误。解决方法：重复作业，点击线再标注。（五）尚未解决的问题及其应对策略无三实验三寄存器组及具有移位功能暂存器的设计与实现 （一）总体设计3.1.1问题分析了解寄存器组及暂存器的工作原理和过程，设计出功能完善的寄存器组，并且使暂存器自身能完成逻辑左移、逻辑右移、算术左移、算术右移等数据移位功能，最终实现相应部件，并进行封装调试。1、分析并设计寄存器组及具有移位功能暂存器的基本结构；2、选择芯片及若干元器件进行连接，完成寄存器组及具有移位功能暂存器的设计，并实现部件的封装；3、对设计出的寄存器组进行测试

36、，检查寄存器组是否能够正确完成数据的存储及读取；4、对设计出的暂存器进行测试，检查暂存器是否能进行数据的暂存和读取，并检测数据移位功能是否正确。期件介绍：通用寄存器组（General Registers）是为了提供进行主机系统设计时所需要的寄存器而设计的。通用寄存器组采用具有三态输出功能的两片 4 位片的74LS670，通过并联组合，构成 4 字8 位的寄存器组。3.1.2总体方案设计。 1、设计出部件的逻辑原理图，画出部件的逻辑电路布线图；2、拟定测试数据及测试方法；3、检测模拟仿真测试结果的正确性；4、对设计出的部件进行封装，并写出封装后芯片的功能表。（二）详细设计3.2.1每个模块的功能

37、具有移位功能的暂存器 存储功能 具有移位功能的暂存器 移位功能 3.2.2入出信息寄存器输入寄存器输出3.2.3处理逻辑通用寄存器组 带有移位功能的暂存器 3.2.4屏幕显示布局设计图74198功能表74244功能表（参考上文）74273功能表（参考上文）74679功能表总线暂存器封装寄存器组封装具有移位功能的暂存器寄存器图（3） 程序编码。寄存器组代码：- Copyright (C) 1991-2008 Altera Corporation- Your use of Altera Corporations design tools, logic functions - and other s

38、oftware and tools, and its AMPP partner logic - functions, and any output files from any of the foregoing - (including device programming or simulation files), and any - associated documentation or information are expressly subject - to the terms and conditions of the Altera Program License - Subscr

39、iption Agreement, Altera MegaCore Function License - Agreement, or other applicable license agreement, including, - without limitation, that your use is for the sole purpose of - programming logic devices manufactured by Altera and sold by - Altera or its authorized distributors. Please refer to the

40、 - applicable agreement for further details.- PROGRAM Quartus II 64-Bit- VERSION Version 8.0 Build 215 05/29/2008 SJ Full VersionLIBRARY ieee;USE ieee.std_logic_1164.all; LIBRARY work;ENTITY no3 IS port(WE : IN STD_LOGIC;WA : IN STD_LOGIC;WB : IN STD_LOGIC;RE : IN STD_LOGIC;RA : IN STD_LOGIC;RB : IN

41、 STD_LOGIC;D0 : IN STD_LOGIC;D1 : IN STD_LOGIC;D2 : IN STD_LOGIC;D3 : IN STD_LOGIC;D4 : IN STD_LOGIC;D5 : IN STD_LOGIC;D6 : IN STD_LOGIC;D7 : IN STD_LOGIC;Q0 : OUT STD_LOGIC;Q1 : OUT STD_LOGIC;Q2 : OUT STD_LOGIC;Q3 : OUT STD_LOGIC;Q4 : OUT STD_LOGIC;Q5 : OUT STD_LOGIC;Q6 : OUT STD_LOGIC;Q7 : OUT STD

42、_LOGIC);END no3;ARCHITECTURE bdf_type OF no3 IS attribute black_box : boolean;attribute noopt : boolean;component 74670_0PORT(WA : IN STD_LOGIC; D1 : IN STD_LOGIC; WB : IN STD_LOGIC; D2 : IN STD_LOGIC; GRN : IN STD_LOGIC; D4 : IN STD_LOGIC; D3 : IN STD_LOGIC; RA : IN STD_LOGIC; RB : IN STD_LOGIC; GWN : IN STD_LOGIC; Q3 : OUT STD_LOGIC; Q4 : OUT STD_LOGIC;