vhdl+序列检测器.doc

1、LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL;ENTITY SCHK ISPORT(DIN, CLK, CLR : IN STD_LOGIC; -串行输入数据位/工作时钟/复位信号AB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -检测结果输出END SCHK;ARCHITECTURE behav OF SCHK ISSIGNAL Q : INTEGER RANGE 0 TO 8 ;SIGNAL D : STD_LOGIC_VECTOR(7 DOWNTO 0); -8 位待检测预置数BEGIND IF DIN = D(7) TH

2、EN Q IF DIN = D(6) THEN Q IF DIN = D(5) THEN Q IF DIN = D(4) THEN Q IF DIN = D(3) THEN Q IF DIN = D(2) THEN Q IF DIN = D(1) THEN Q IF DIN = D(0) THEN Q Q = 0 ;END CASE ;END IF ;END PROCESS ;PROCESS( Q ) -检测结果判断输出BEGINIF Q = 8 THEN AB = “1010“ ; -序列数检测正确，输出 “A“ELSE AB = “1011“ ; -序列数检测错误，输出 “B“END IF ;END PROCESS ;END behav ;