1、 ICN6201 User Guide V0.2 - 1 - ICN6201 User Guide MIPI DSI BRIDGE TO FLATLINKTM LVDS Revision 0.2 NOTICE NOTICENOTICENOTICENOTICE This design and all of its related documentation constitutes valuable and confidential property of Chipone Technology (Beijing) Co., Ltd. It is licensed for use as expres
2、sly stated in the written license Agreement between Chipone Technology (Beijing) Co., Ltd and its customers. Any other use or redistribution of this design and all related documentation is expressly prohibited. This design and all related documentation have been released by Chipone Technology (Beiji
3、ng) Co., Ltd to its customers under a Non Disclosure Agreement (NDA). Disclosure of this design outside of this agreement is expressly prohibited. NOTICE NOTICENOTICENOTICENOTICE Chipone Technology (Beijing) Co., Ltd 13th Floor, Test Tower, Building 4, 31 Middle North Third Ring Rd., Haidian Distric
4、t, Beijing, 100088 PRC Contact: Simon Liu Email: simon_ ICN6201 User Guide V0.2 - 2 - Revision History Rev Date Author Description 0.1 2013-07-31 Simon_Liu WangGang Initial version 0.2 2013-08-30 Simon_Liu WangGang Change figure format of reference schematic to fit Zoom in/out ICN6201 User Guide V0.
5、2 - 3 - Table of Contents 1 Overview . - 5 - 2 Implementation Guidelines . - 6 - 2.1 MIPI signal pins - 6 - 2.2 LVDS signal pins . - 6 - 2.3 REFCLK PIN - 6 - 2.4 VCORE PIN - 6 - 2.5 EN PIN . - 6 - 2.6 ADDR_SEL PIN - 7 - 2.7 TEST_EN the totally maximum input bandwidth is 4Gbps; The LVDS output 18 or
6、24 bits pixel with 25MHz to 154MHz, by VESA or JEIDA format. ICN6201 adopts QFN40 and QFN 48pins package. ICN6201 User Guide V0.2 - 6 - 2 Implementation Guidelines 2.1 MIPI signal pins DA0P/N, DA1P/N, DA2P/N, DA3P/N, DACP/N are MIPI high speed signals, which max bit rate is 1Gbps, so it is preferred
7、 to avoid via when routing. Each pair *P/N should be routed together with controlled-differential 100- impedance. The unused MIPI pins can be left unconnected or driven to LP11 or LP00. 2.2 LVDS signal pins A_Y0P/N, A_Y1P/N, A_Y2P/N, A_Y3P/N, A_CLKP/N are LVDS output high speed signals, so it is pre
8、ferred to avoid via when routing. Each pair *P/N should be routed together with controlled-differential 100- impedance. The unused LVDS pins should be left unconnected. Note: When power down the unused LVSD channel, the output is pull down to GND with internal 2K resister. The polarity of each pair
9、of LVDS signals can be swapped by control registers. Each pair of LVDS can also be swapped by control registers. 2.3 REFCLK PIN For package QFN40, there is only one REFCLK pin(#22), but for package QFN48, there are 2 REFCLK pin(#11 and #26), each REFCLK can be as the reference clk of LVDS output. Th
10、ese pins receive AC coupled clock signals, which frequency is typical 26MHz. Please note: if any one REFCLK pin is not used, this pin should be connected to GND. 2.4 VCORE PIN This pin outputs 1.2V from the internal voltage regulator. This pin MUST have at least one 1uF and at least one 0.01uF exter
11、nal capacitor to GND. 2.5 EN PIN ICN6201 is reset by control pin EN to Low. It is critical to transition the EN input from a low to a high level after the Vcc supply has reached the minimum operating voltage as following figure 2-1. ICN6201 User Guide V0.2 - 7 - Figure 2-1 timing between EN and VCC
12、To achieve the required timing, an approximately 200nF capacitor as a reasonable first estimate is needed. The internal pull-up resister is about 200K. Figure 2-2 EN implement with external capacitor 2.6 ADDR_SEL PIN The pin ADDR_SEL control the I2C slave s device address. When this pin is connected
13、 to GND, the I2C device address is 0x2C; When this pin is connected to VDD, the I2C device address is 0x2D. 2.7 TEST_EN & BIST_EN PIN These two pins are not used for normal function. They can be connected to GND or left unconnected. 2.8 GPIO_0 & GPIO_1 & ATEST PIN These three pins are reserved for d
14、ebug function. They can be left unconnected. 2.9 IRQ This pin is interrupt pin. If it is not used, it can be left unconnected. ICN6201 User Guide V0.2 - 8 - 2.10 SCL & SDA PIN These two pins are I2C signals. They should be connected to I2C master with pull-up resister if I2C function is used. If these two pins are not used, they can be left unconnected. ICN6201 User Guide V0.2 - 9 - 3 Reference schematics 3.1 Reference Schematics for QFN48 Figure 3-1 Reference schematic for QFN48 ICN6201 User Guide V0.2 - 10 - 3.2 Reference Schematics for QFN40 Figure 3-2 Reference schematic for QFN40
