1、 AEC - Q100 - Rev-H September 11, 2014 FAILURE MECHANISM BASED STRESS TEST QUALIFICATION FOR INTEGRATED CIRCUITS Component Technical CommitteeAutomotive Electronics CouncilAEC - Q100 - REV-H September 11, 2014 Component Technical CommitteeAutomotive Electronics CouncilTABLE OF CONTENTS AEC-Q100 Fail
2、ure Mechanism Based Stress Test Qualification for Integrated Circuits Appendix 1: Definition of a Qualification Family Appendix 2: Q100 Certification of Design, Construction and Qualification Appendix 3: Plastic Package Opening for Wire Bond Testing Appendix 4: Minimum Requirements for Qualification
3、 Plans and Results Appendix 5: Part Design Criteria to Determine Need for EMC Testing Appendix 6: Part Design Criteria to Determine Need for SER Testing Appendix 7 AEC-Q100 and the Use of Mission Profiles Attachments AEC-Q100-001: WIRE BOND SHEAR TEST AEC-Q100-002: HUMAN BODY MODEL (HBM) ELECTROSTAT
4、IC DISCHARGE (ESD) TEST AEC-Q100-003: MACHINE MODEL (MM) ELECTROSTATIC DISCHARGE (ESD) TEST (DECOMMISSIONED) AEC-Q100-004: IC LATCH-UP TEST AEC-Q100-005: NONVOLATILE MEMORY WRITE/ERASE ENDURANCE, DATA RETENTION, AND OPERATIONAL LIFE TEST AEC-Q100-006: ELECTRO-THERMALLY INDUCED PARASITIC GATE LEAKAGE
5、 (GL) TEST (DECOMMISSIONED) AEC-Q100-007: FAULT SIMULATION AND TEST GRADING AEC-Q100-008: EARLY LIFE FAILURE RATE (ELFR) AEC-Q100-009: ELECTRICAL DISTRIBUTION ASSESSMENT AEC-Q100-010: SOLDER BALL SHEAR TEST AEC-Q100-011: CHARGED DEVICE MODEL (CDM) ELECTROSTATIC DISCHARGE (ESD) TEST AEC-Q100-012: SHO
6、RT CIRCUIT RELIABILITY CHARACTERIZATION OF SMART POWER DEVICES FOR 12V SYSTEMS AEC - Q100 - REV-H September 11, 2014 Component Technical CommitteeAutomotive Electronics CouncilRevision Summary This informative section briefly describes the changes made in the AEC-Q100 Rev-H document, compared to pre
7、vious document version, AEC-Q100 Rev-G (May 14, 2007). Punctuation and text improvements are not included in this summary. Section 1.2.1 Automotive Reference Documents: Added reference to AEC-Q005 Pb-Free Requirements NEW Section 1.2.4 Decommissioned Reference Documents: Added new section providing
8、guidance on elimination of AEC-Q100-003 Machine Model ESD (removed due to industry test obsolescence) and Q100-006 Electrothermally Induced Gate Leakage (removed due to lack of industry need as a qualification test) Section 1.3.1 AEC Q100 Qualification: Added recommendation that passing ESD voltage
9、level be specified in supplier datasheet with footnote on any pin exceptions NEW Section 1.3.2 AEC Certification: Added new definition clarifying that AEC-Q100 “certification” does not exist, suppliers perform qualification testing according to AEC standards Section 1.3.4 Definition of Part Operatin
10、g Temperature Grade: Added new Table 1 defining part operating temperature grades and guidance on use of temperature (e.g., endpoint, junction) during tests; eliminated Grade 4 (0C to +70C) entry NEW Section 1.3.5 Capability Measure, Cpk: Added new definition and reference to AEC-Q003 Characterizati
11、on document Section 2.2 Precedence of Requirements: Added clarification to Purchase Order and Device Specification entries Section 2.3.1 Definition of Generic Data: Moved existing Table 1, Part Qualification/Requalification Lot Requirements, and portion of section text to Appendix 1 Definition of a
12、Product Qualification Family Section 2.3.2 Time Limit for Acceptance of Generic Data: Added text on use of diagram in Figure 1 Section 2.4.1 Lot Requirements: Added statement that deviation from Table 2 requires technical explanation Section 2.5 Definition of Test Failure After Stressing: Added stat
13、ement on EOS Section 3.1.1 Qualification of A New Device Manufactured in A Currently Qualified Family: Deleted this entire section, subject is covered in Appendix 1. Section 3.2.3 Criteria for Passing Requalification: Modified text to provide better guidance on AEC-Q100 requalification NEW Section 3
14、.3 Qualification of A Pb-Free Device: Added new section with requirements for Pb-Free devices and references to AEC-Q005 Pb-Free Requirements document Figure 2 Qualification Test Flow: o Test Group A: Removed statement of PC before PTC o Test Group B: Corrected test temperature order for post-HTOL t
15、esting to Room, Cold, added legacy test temperature note; eliminated Grade 4 entry o Test A6 High Temperature Storage Life: Added reference to Ta (ambient temperature) o Test A7 High Temperature Operating Life: Removed 408 hour test duration option; added notes regarding use of Ta (ambient temperatu
16、re) and Tj (junction temperature) o Test C1 Wire Bond Shear: Removed Ppk requirement; modified Cpk accept criteria to Cpk1.67; added reference to AEC-Q003 o Test C2 Wire Bond Pull: Removed Ppk requirement; modified Cpk accept criteria to Cpk1.67; added reference to AEC-Q003 o Test C3 Solderability:
17、Added reference to J-STD-002D and statement on use of dry bake AEC - Q100 - REV-H September 11, 2014 Component Technical CommitteeAutomotive Electronics CouncilRevision Summary (continued) Table 2 Qualification Test Methods (continued): o Test C4 Physical Dimension: Removed Ppk requirement; modified
18、 Cpk accept criteria to Cpk1.67; added reference to AEC-Q003 o Test C5 Solder Ball Shear: Removed Ppk requirement; modified Cpk accept criteria to Cpk1.67; added reference to AEC-Q003 o Test E2 Electrostatic Discharge Human Body Model/Machine Model: Eliminated Machine Model (MM) ESD entry; added ref
19、erence to Section 1.3.1 o Test E3 Electrostatic Discharge Charged Device Model: Added reference to Section 1.3.1 o Test E5 Electrical Distribution: Added Cpk1.67 accept criteria and reference to AEC-Q003 o Eliminated Test E8 Electrothermally Induced Gate Leakage entry o NEW Test E12 Lead (Pb) Free:
20、Added new test entry o Test F1 Part Average Testing: Modified Additional Requirements providing guidance on sample sizes and accept criteria o Test F2 Statistical Bin/Yield Analysis: Modified Additional Requirements providing guidance on sample sizes and accept criteria o Test G1 Mechanical Shock: M
21、odified sample size/lot and number of lots o Test G2 Variable Frequency Vibration: Modified sample size/lot and number of lots o Test G3 Constant Acceleration: Modified sample size/lot and number of lots o Test G4 Gross/Fine Leak: Modified sample size/lot and number of lots o Test G8 Internal Water
22、Vapor: Modified sample size/lot o Table 2 Legend: Added Note L reference for Pb-Free devices Table 3 Process Change Qualification Guidelines for the Selection of Tests: Removed MM (Machine Model) ESD and GL (Gate Leakage) entries; added LF (Lead Free) entry Appendix 1 Definition of a Product Qualifi
23、cation Family: Complete revision o NEW Section A1.1 Product: Added new section and text o NEW Section A1.4 Qualification/Requalification Lot Requirements: Relocated original AEC-Q100 Rev G Table 1 to Appendix 1 and renumbered as Table A1.1 o Revised Table A1.1 Part Qualification/Requalification Lot
24、Requirements: Deleted row titled “A new part that has some applicable generic data”; added NEW entry where “The part to be qualified is slightly more complex” o NEW Table A1.2 Examples for Generic Data Use: Added new Table and content Appendix Template 4A AEC-Q100 Qualification Test Plan: o Test C3,
25、 SD - Solderability: Added reference to J-STD-002D and requirement of steam aging o Test E2, HBM/MM ESD Human Body/machine Model: Eliminated MM entry o Test E8, GL Electrothermally Induced Gate Leakage: Eliminated GL entry o Tests G1-G4, MECH Hermetic Package Tests: Modified sample size and lot requ
26、irements Appendix Template 4B AEC-Q100 Generic Data: o Test C3, SD: Added reference to J-STD-002D and requirement of steam aging o Test E2, HBM/MM: Eliminated MM entry o Test E8, GL: Eliminated GL entry o Test G1, MS: Modified sample size and lot requirements o Test G2, VFV: Modified sample size and
27、 lot requirements o Test G3, CA: Modified sample size and lot requirements o Test G4, GFL: Modified sample size and lot requirements o Complete revision of Generic Data Part Attributes Section NEW Appendix 7 Guideline on Relationship of Robustness Validation to AEC-Q100: Added NEW Section and text,
28、including NEW Figures A7.1 the Tj of the test (measured or calculated ) should be available. 2) Tj may be used instead of Ta when performing HTOL provided that Tj of the device under HTOL conditions is equal to or higher than the Tj maximum operating (Tjopmax) of the particular device, but below the
29、 absolute maximum Tj. 3) If Tj is used to set the HTOL conditions, the minimum stress of 1000 hours at the Ta of the device is to be shown using activation energy of 0.7ev or other value technically justified. 4) Vcc (max) at which dc and ac parametrics are guaranteed. Thermal shut-down shall not oc
30、cur during this test. TEST before and after HTOL at room, cold, and hot temperature (in that order). Early Life Failure Rate ELFR B2 H, P, B, N, G 800 3 0 Fails AEC Q100-008 Devices that pass this stress can be used to populate other stress tests. Generic data is applicable. TEST before and after EL
31、FR at room and hot temperature. NVM Endurance, Data Retention, and Operational Life EDR B3 H, P, B, D, G, K 77 3 0 Fails AEC Q100-005 TEST before and after EDR at room and hot temperature. Sample size and lot requirement applies to EACH of the NVM tests per Q100-005. AEC - Q100 - REV-H September 11,
32、 2014 Page 13 of 42 Component Technical CommitteeAutomotive Electronics CouncilTable 2: Qualification Test Methods (continued) TEST GROUP C PACKAGE ASSEMBLY INTEGRITY TESTS STRESS ABV # NOTES SAMPLE SIZE / LOT NUMBER OF LOTS ACCEPT CRITERIA TEST METHOD ADDITIONAL REQUIREMENTS Wire Bond Shear WBS C1
33、H, P, D, G 30 bonds from a minimum of 5 devices CPK 1.67 AEC Q100-001 AEC Q003 At appropriate time interval for each bonder to be used. Wire Bond Pull WBP C2 H, P, D, G CPK 1.67 or 0 Fails after TC (test #A4) MIL-STD883 Method 2011 AEC Q003 Condition C or D. For Au wire diameter 1mil, minimum pull s
34、trength after TC = 3 grams. For Au wire diameter 95% lead coverage JEDEC JESD22-B102 or JEDEC J-STD-002D If burn-in screening is normally performed on the device before shipment, samples for SD must first undergo burn-in. Perform 8 hour steam aging prior to testing (1 hour for Au-plated leads). The
35、customer can request justification for using dry bake in place of steam aging. Physical Dimensions PD C4 H, P, D, G 10 3 CPK 1.67 JEDEC JESD22-B100 and B108 AEC Q003 See applicable JEDEC standard outline and individual device spec for significant dimensions and tolerances. Solder Ball Shear SBS C5 B
36、 5 balls from a min. of 10 devices 3 CPK 1.67 AEC Q100-010 AEC Q003 PC thermally (two 220C reflow cycles) before integrity (mechanical) testing. Refer to J-STD-020 for Pb-free reflow profiles to be used for this test. Lead Integrity LI C6 H, P, D, G 10 leads from each of 5 parts 1 No lead breakage o
37、r cracks JEDEC JESD22-B105 Not required for surface mount devices. Only required for through-hole devices. TEST GROUP D DIE FABRICATION RELIABILITY TESTS STRESS ABV # NOTES SAMPLE SIZE / LOT NUMBER OF LOTS ACCEPT CRITERIA TEST METHOD ADDITIONAL REQUIREMENTS Electromigration EM D1 - - - - - The data,
38、 test method, calculations and internal criteria should be available to the user upon request for new technologies. Time Dependent Dielectric Breakdown TDDB D2 - - - - - The data, test method, calculations and internal criteria should be available to the user upon request for new technologies. AEC -
39、 Q100 - REV-H September 11, 2014 Page 14 of 42 Component Technical CommitteeAutomotive Electronics CouncilTable 2: Qualification Test Methods (continued) TEST GROUP D DIE FABRICATION RELIABILITY TESTS (CONTINUED) STRESS ABV # NOTES SAMPLE SIZE / LOT NUMBER OF LOTS ACCEPT CRITERIA TEST METHOD ADDITIO
40、NAL REQUIREMENTS Hot Carrier Injection HCI D3 - - - - - The data, test method, calculations and internal criteria should be available to the user upon request for new technologies. Negative Bias Temperature Instability NBTI D4 - - - - - The data, test method, calculations and internal criteria shoul
41、d be available to the user upon request for new technologies. Stress Migration SM D5 - - - - - The data, test method, calculations and internal criteria should be available to the user upon request for new technologies. TEST GROUP E ELECTRICAL VERIFICATION TESTS STRESS ABV # NOTES SAMPLE SIZE / LOT
42、NUMBER OF LOTS ACCEPT CRITERIA TEST METHOD ADDITIONAL REQUIREMENTS Pre- and Post-Stress Function/Parameter TEST E1 H, P, B, N, G All All 0 Fails Test program to supplier data sheet or user specification Test is performed as specified in the applicable stress reference and the additional requirements
43、 in Table 2 and illustrated in Figure 2. Test software used shall meet the requirements of Q100-007. All electrical testing before and after the qualification stresses are performed to the limits of the individual device specification in temperature and limit value. Electrostatic Discharge Human Bod
44、y Model HBM E2 H, P, B, D See Test Method 1 Target: 0 Fails 2KV HBM (Classification 2 or better) AEC Q100-002 TEST before and after ESD at room and hot temperature. Device shall be classified according to the maximum withstand voltage level. Device levels 1.67 AEC Q100-009 AEC Q003 Supplier and user
45、 to mutually agree upon electrical parameters to be measured and accept criteria. TEST at room, hot, and cold temperature. Fault Grading FG E6 - - - AEC Q100-007 unless otherwise specified AEC Q100-007 For production testing, see Q100-007 for test requirements. Characterization CHAR E7 - - - - AEC Q
46、003 To be performed on new technologies and part families. Electromagnetic Compatibility EMC E9 - 1 1 - SAE J1752/3 Radiated Emissions See Appendix 5 for guidelines on determining the applicability of this test to the device to be qualified. This test and its accept criteria is performed per agreeme
47、nt between user and supplier on a case-by-case basis. Short Circuit Characterization SC E10 D, G 10 3 0 Fails AEC Q100-012 Applicable to all smart power devices. This test and statistical evaluation (see Section 4 of Q100-012) shall be performed per agreement between user and supplier on a case-by-c
48、ase basis. Soft Error Rate SER E11 H, P, D, G 3 1 - JEDEC Un-accelerated: JESD89-1 or Accelerated: JESD89-2 3 lots ED AC(E) and 1 lot HTOL minimum on AnCE in addition to below for all cases Previously Qualified Scenario (Existing Generic Data) Case Description Product Fab Site Assembly Site Lots of
49、Generic Data Available Use Options of Generic Data 1 B from a different product family B C E 3 No Option 3 lots AnCE (new test) 2A B from a different product family B C F 3 No Option 3 lots using An (new test) 2B D E 3 No Option 3 lots AnCE (new test) 3 Different Fab Process and different site as A1 Different Assembly and different site as A1 A1 D F 3 No Option 3 lots
