1、第四章 时序逻辑电路的VHDL设计,第四章 时序逻辑电路的VHDL设计,时序逻辑块的设计 同步时序系统 算法状态机ASM设计方法 状态机的VHDL实现,一、时序逻辑模块的设计,D触发器,ENTITY dff IS PORT ( d : in std_logic;clk ,clrn: in std_logic;q : out std_logic); END dff; ARCHITECTURE behavior OF dff IS BEGINPROCESS (clk,clrn)BEGINIF(clrn=0) THEN q=0;ELSIF clkevent and clk=1 THENq = d;E
2、ND IF;END PROCESS; END behavior;,异步复位,Clk上升沿触发,带wait语句的D触发器,ENTITY dff IS PORT ( d : in std_logic;clk : in std_logic;q : out std_logic); END dff;ARCHITECTURE behavior OF dff IS BEGINPROCESS BEGINwait until clk = 1;q = d;END PROCESS; END behavior;,没有敏感表,wait until：作用等同于敏感表,多少个触发器?,SIGNAL a, b : std_l
3、ogic; BEGINPROCESS (clk)BEGINIF rising_edge(clk) THENa = d;b = a;q = b;END IF;END PROCESS;,多少个触发器?,SIGNAL a, b : std_logic; BEGINPROCESS (clk)BEGINIF rising_edge(clk) THENa = d;b = a;END IF;END PROCESS;q = b;,b 到 q 赋值不是边沿敏感 ，因为不是在IF-THEN语句中,多少个触发器?,ARCHITECTURE reg1 OF reg1 IS BEGINPROCESS (clk)VARI
4、ABLE a, b : std_logic;BEGINIF rising_edge(clk) THENa := d;b := a;q = b;END IF;END PROCESS; END reg1;,变量立即赋值 信号在时钟边缘赋值,时序电路的不同表述,PROCESS (CLK)BEGINIF CLK = 1 THEN Q = D ;END IF; END PROCESS,利用进程的启动特性产生对CLK的边沿检测,时序电路的不同表述,PROCESS (CLK，D) BEGINIF CLK = 1THEN Q = D ; END IF; END PROCESS ;,电平触发型寄存器,锁存器,L
5、IBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY latch IS PORT ( data : IN std_logic;gate : IN std_logic;q : OUT std_logic); END latch; ARCHITECTURE behavior OF latch IS BEGINPROCESS (data, gate)BEGINIF gate = 1 THENq = data;END IF;END PROCESS; END behavior;,敏感表包括所有输入,移位寄存器,ENTITY sipo isgeneric (n: natural :=8);port (a, clk: in std_logic;q: out std_logic_vector(n-1 downto 0); END sipo; ARCHITECTURE rt1 OF sipo IS BEGINP0: PROCESS (clk) isVARIABLE reg: std_logic_vector(n-1 downto 0);BEGINIF rising_edge(clk) THENreg:= reg (n-2 downto 0) ,&,如何实现右移？,课堂练习,设计8位PISO移位寄存器,
