1、,module test_def(a,b,c,d,e,dout);input a,b,c,d,e;output dout;wire dout;define expression a+b+c+dassign dout=expression + e;endmodule,module aaa(a,b,out);input a,b;output out;wire out; assign out=ab;endmodule,/include “aaa.v“ module test_inc(c,d,e,out);input c,d,e;output out;wire out_a;wire out;aaa u
2、1(.a(c),.b(d),.out(out_a); assign out=e endmodule,module add_n(a,b,cin,sum,cout);parameter n=4;input n-1:0 a,b;input cin;output n-1:0 sum;output cout;assign cout,sum=1b0,a+b+cin;endmodule,方法1,module add_8(in_a,in_b,cin,sum,cout);input 7:0 in_a,in_b;input cin;output 7:0 sum;output cout;add_n #8 u1(in
3、_a,in_b,cin,sum,cout);endmodule,方法2,module add_8(in_a,in_b,cin,sum,cout);input 7:0 in_a,in_b;input cin;output 7:0 sum;output cout;defparam u1.n=8;add_n u1(in_a,in_b,cin,sum,cout);endmodule,module add_n(clk,a,b,cin,sum,cout);parameter n=4;input clk;input n-1:0 a,b;input cin;output n-1:0 sum;output co
4、ut;reg n-1:0 sum;reg cout;reg n-1:0 tmpa,tmpb;reg tmpc;,always (posedge clk)begintmpb=a;tmpb=b;tmpc=cin;endalways (posedge clk)begincout,sum=1b0,tmpa+tmpb+tmpc;end endmodule,module add_8(clk,in_a,in_b,cin,sum,cout);input 7:0 in_a,in_b;input cin,clk;output 7:0 sum;output cout;defparam u1.n=8;add_n u1(clk,in_a,in_b,cin,sum,cout);endmodule,
