1、 第九章 虚拟器件与虚拟接口模型213第九章 虚拟器件和虚拟接口模型以及它们在大型数字系统设计中的作用前言宏单元(Macrocells 或 Megacells)或核(Cores)是预先设计好的，其功能经过验证的、由总数超过 5000个门构成的一体化的电路模块，这个模块可以是以软件为基础的，也可以是以硬件为基础的。这就是我们在第一章的 1.5.3和 1.5.4节中讨论过的软核和硬核。所谓虚拟器件(Virtual Chips)也就是用软核构成的器件，即用 Verilog HDL或VHDL语言描述的常用大规模集成电路模型。 在新电路研制过程中，借助 EDA综合工具，软核和虚拟器件可以很容易地与其它外
2、部逻辑结合为一体，从而大大扩展了设计者可选用的资源。掌握软核和虚拟器件（也称接口模型）的重用技术可大大缩短设计周期，加快高技术新芯片的投产和上市 。而所谓虚拟接口模型则是用系统级 Verilog HDL或VHDL语言描述的常用大规模集成电路（如 ROM和 RAM）或总线接口的行为模型等，往往是不可综合的，也没有必要综合成具体电路，但其所有对外的性能与真实的器件或接口完全一致，在仿真时可用来代替真实的部件，用以验证所设计的电路（必须综合的部分）是否正确。在美国和电子工业先进的国家，各种微处理器芯片（如 8051）、通用串行接口芯片（如 8251）、中断控制器芯片（如 8259）、并行输入输出接口
3、芯片(PIO)、直接存储器存取芯片（DMA）、数字信号处理芯片(DSP)、RAM 和 ROM芯片和 PCI总线控制器芯片以及 PCI总线控制接口等都有其相对应的商品化的虚拟器件和虚拟接口模型可供选用。虚拟器件往往只提供门级和 RTL级的 Verilog HDL或 VHDL源代码，而虚拟接口模型往往提供系统级代码。这是因为门级和 RTL级的 Verilog HDL或 VHDL是可综合的，它与具体的逻辑电路有着精确的对应关系。近年来在现代数字系统设计领域中发展最快的一个部门就是提供虚拟器件和虚拟接口模型的设计和服务。 目前国际上有一个叫作虚拟接口联盟(VSIA)的组织，它是协调虚拟器件和虚拟接口模
4、型的设计标准和服务工作的国际组织。虚拟器件和虚拟接口模型必须符合通用的工业标准和达到一定的质量水准，才能发布。这对选用虚拟器件和虚拟接口模型来设计复杂系统的工程师们无疑有很大的帮助。如果他们采用虚拟器件和虚拟接口模型技术来设计复杂的数字系统必将大大缩短设计周期并提高设计的质量，也为千万门级单片系统的实现铺平了道路。第九章 虚拟器件与虚拟接口模型2149.1虚拟器件和虚拟接口模块的供应商在这一节中我们列出一些虚拟器件和接口的供应商的 E-mail地址及它们提供的产品和服务供读者参考：公司名 虚拟器件类型 所用语言 加密否 语言级别American Microsystem电子信箱：算术运算函数异步
5、同步 FIFODSP微处理器UART和 USARTsRAM 和 ROMVerilogVHDL不 门级RTL级第九章 虚拟器件与虚拟接口模型215ARMSemiconductor电子信箱：微处理器：8031,8032,8051通信器件：8530总线控制器：82365(PCMCIA Host i/f)Verilog 可选 系统级（只可用于仿真）Scenix Semiconductor电子信箱：控制器：NS COP8PCI arbiter,master第九章 虚拟器件与虚拟接口模型218input nconvst; / A/D 启动脉冲 ST，即上图中 output nbusy; / A/D 工作标
6、志，即上图中 output data; / 数据总线，从 AD.DATA文件中读取数据后经端口输出reg7:0 databuf,i; / 内部寄存器reg nbusy;wire7:0 data;reg7:0 data_mem0:255;reg link_bus;integer tconv,t5,t8,t9,t12;integer wideth1,wideth2,wideth; /时间参数定义(依据 AD7886手册)：always (negedge nconvst)begintconv =9500+$random%500; /(type 950, max 1000）Conversion Tim
7、et5 =$random%1000; /(max 100) CONVST to BUSY Propagation Dlay/ CL = 10pft8 = 200; /(min 20) CL=20pf Data Setup Time Prior to BUSY/(min 10) CL=100pft9 = 100+$random%900; /(min 10, max 100) Bus Relinquish Time After /CONVSTt12 = 2500; /(type) BUSY High to CONVST Low, SHA Acquisition Timeendinitialbegi
8、n $readmemh(“adc.data“,data_mem); /从数据文件 adc.data中读取数据 i = 0;nbusy = 1; link_bus = 0;end assign data = link_bus? databuf:8bzz; /三态总线/*-在信号 nconvst的负跳降沿到来后，隔 t5秒 nbusy信号置为低，tconv 是 AD将模拟信号转换为数字信号的时间，在信号 nconvst的正跳降沿到来后经过 tconv时间后，输出nbusy信号变为高。 -*/ always (negedge nconvst) 第九章 虚拟器件与虚拟接口模型219fork#t5 nb
9、usy =0;(posedge nconvst)begin #tconv nbusy=1;end join/*- nconvst信号的下降沿触发，经过 t9 延时后，把数据总线输出关闭置为高阻态，如图示。nconvst信号的上升沿到来后，经过（tconv - t8)时间，输出一个字节（8 位数据）到databuf， 该数据来自于 data_mem。而 data_mem中的数据是初始化时从数据文件 AD.DATA中读取的。 此时应启动总线的三态输出。 -*/always (negedge nconvst) begin(posedge nconvst)begin #(tconv-t8) datab
10、uf=data_memi; endif(wideth 500) beginif(i=255) i=0;else i=i+1;end else i = i;end/在模数转换期间关闭三态输出，转换结束时启动三态输出always (negedge nconvst)fork#t9 link_bus = 1b0; /关闭三态输出，不允许总线输出(posedge nconvst)begin #(tconv-t8) link_bus=1b1; endjoin/*-当 nconvst输入信号的下一个转换的下降沿与 nbusy信号上升沿之间时间延迟小于 t12时，将会出现警告信息，通知设计者请求转换的输入信号
11、频率太快，A/D 器件转换速度跟不上。仿真模型不仅能够实现硬件电路的输出功能，同时能够对输入信号进行检测，当输入信号不符合手册要求时，显示警告信息。-*/第九章 虚拟器件与虚拟接口模型220/ 检查 A/D启动信号的频率是否太快always (posedge nbusy)begin#t12;if (!nconvst) begin $display(“Warning! SHA Acquisition Time is too short!“);end/ else $display(“ SHA Acquisition Time is enough! “);end/ 检查 A/D启动信号的负脉冲宽度是
12、否足够和太宽always (negedge nconvst)beginwideth=$time;(posedge nconvst) wideth=$time-wideth;if (wideth 10000)begin$display(“nCONVST Pulse Width = %d“,wideth);$display(“Warning! nCONVST Pulse Width is too narrow or too wide!“);/$stop;endendendmodule/+对商业化的虚拟模块有着严格的要求，不但要求在系统设计的仿真中能完全来代替真实的器件，而且还希望能提示产生错误的原
13、因。虚拟模块的精确与否，直接决定设计的成败。 ASIC 的投片成本很高，编写虚拟模块时任何小的疏忽都有可能造成投片的失败，造成大量资金的浪费。因此编写这样的模块是一件复杂而细致的工作，需要极其认真的工作态度和作风，必须认真对待。为了简单起见，本节介绍的模块只具有AD7886的一部分功能，所以还不能称为 AD7886完整的虚拟模块。第九章 虚拟器件与虚拟接口模型221通过上述简单的例子我们能了解一个虚拟模块是如何设计的，对大多数的电路系统工程师来说，我们尽量利用商业化的虚拟模块来设计自己的电路系统。只有在没有办法得到商业化的虚拟模块时，才利用器件手册来编写虚拟模块，因为编写精确的虚拟模块需要花费
14、很多时间和精力。9.3 虚拟接口模块的实例下面我们介绍两个常用的大规模集成芯片：通用串行收发控制器 USART8251和Intel8085 微处理器 CPU的虚拟接口模块。这两个用 Verilog HDL描述的虚拟接口的行为模块是由 Verilog 语言的创始人 P.R.Moorby 和 D.E. Thomas合作编写的( 这是我们从 Internet网络上下载得到的 )。因为商品化的虚拟器件和虚拟接口模型是知识产权（简称 IP），必须保证设计所需的参数绝对正确，因此价格非常昂贵，不可能免费得到。下面的模块从严格意义上说来并非是真正的虚拟接口模型，因为它们并不对用户设计的成败负责。把它们列在这
15、里只是拿它们作为学习编写较复杂的 Verilog HDL行为模块的样本而已。例 1.“商业化”的虚拟模块之一：Intel USART 8251A (通用串行异步收发器芯片) 在 8251A虚拟接口模块程序的原始材料上有下面这样一段话：/*CADENCE DESIGN SYSTEMS, Inc. does not guarantee the accuracy or completeness of this model. Anyone who using this does so at their own risk.*/显然这一模块只是一个仅供参考的实例，在本教材上我们姑且把它当作虚拟接口模型来看
16、待，因为它的 Verilog HDL程序是严格地按照 8251A的说明书而编写的。读者可以对照 8251A的说明书仔细阅读这一程序，下面就是 USART8251A虚拟模块的 Verilog HDL程序，供读者参考：第九章 虚拟器件与虚拟接口模型222/*通用串行异步收发器 8251 的 Verilog HDL 源代码注意：作者不能保证本模块的完整和精确，使用本模块者如遇问题一切责任自负*/module I8251A ( dbus, rcd, gnd, txc_, write_, chipsel_, comdat_, read_, rxrdy, txrdy, syndet, cts_, txe,
17、 txd, clk, reset, dsr_,rts_,dtr_,rxc_,vcc); /* timing constants ,for A. C. timing check, only non-zero times are specified,in nano-sec */ /* read cycle */ define TRR 250 define TRD 200 define TDF 100 / max. time used /* write cycle */ define TWW 250 define TDW 150 define TWD 20 define TRV 6 / in ter
18、ms of clock cycles /* other timing */ define TTXRDY 8 / 8 clock cycle input rcd, /receive data rxc_, /receive clock txc_, /transmit clock chipsel_, /chip selected when low comdat_, /command /data_ select read_,write_, dsr_, / data set ready cts_, / clear to send reset, / reset when high clk, / at le
19、ast 30 times of the transmit/rexeibe data bit rates gnd, vcc; output rxrdy, /receive data ready when high txd, /transmit data lone txrdy, /transmit buffer ready to accept another byte to transfer txe, / transmit buffer empty 第九章 虚拟器件与虚拟接口模型223rts_, / request to send dtr_; / data terminal ready inout
20、7:0 dbus; inout syndet; /outside synchonous detect or output to indicate syn det supply0 gnd; supply1 vcc; reg txd, rxrdy, txe, dtr_, rts_; reg 7:0 receivebuf, rdata, status; /*ADD BY FWN reg 3:0 dflags; reg 7:0 instance_id; reg read,chipel_; /*reg recvdrv, statusdrv; / if recvdrv 1 dbus is driven b
21、y rdata assign dbus = recvdrv ? rdata : 8bz; /*:,-; assign dbus = statusdrv ? status : 8bz ; /*:-; assign abscent reg 7:0 command, tdata_out, / data being transmitted serially tdata_hold, / data to be transmitted next if tdata_out is full sync1,sync2, / synchronous data bytes modreg; and (txrdy, sta
22、tus0, command0, cts_); reg transmitter_reset, / set to 1 upon a reset ,cleared upon write data tdata_out_full, / 1 if data in tdata_out has not been transmitted. tdata_hold_full, / 1 if data in tdata_hold has not been transferred / to tdata_out for serial transmission. tdata_hold_cts; / 1 if tdata_h
23、old_full and it was cts when data / was transferred to tdata_hold. / 0 if tdata_hold is empty or is full but was / filled while it was not cts. reg tdata_out_wait; / 0 if a stop bit was just sent and we do not 第九章 虚拟器件与虚拟接口模型224need / to wait for a negedge on txc before transmitting reg 7:0 syncmask
24、; nmos syndet_gate1(syndet,status6, modreg6); reg sync_to_receive; / 1(2) if looking for 1st(2nd) sync on rxd reg syncs_received; / 1 if sync chars received, 0 if lookinf for syncreg rec_sync_index; / indicating the syn. character to be matched integer breakcount_period; / number of clock periods to
25、 count as break reg sync_to_transmit; /1(2) if 1st(2nd) sync char should be sent next reg 7:0 data_mask; /masks off the data bits (if char size is not 8) / temporary registers reg 1:0 csel; /indicates what next write means if comdat_=1: /(0=mode instruction ,1=sync1,2=sync2,3=command) reg 5:0 baudmx
26、, tbaudcnt, rbaudcnt; / baud rate reg7:0 tstoptotal; / no. of tranmit clock pulses for stop bit (0 if sync mode reg3:0 databits; / no. of data bits in a character (5,6,7 or 8) reg rdatain; / a data byte is read in if 1 reg was_cts_when_received; / 0:if cts_ was high when char was received / 1:if cts
27、_ was low wheb char was received / (and so char was sent before shutdown) event resete, start_receiver_e,hunt_sysnc1_e; reg receive_in_progress; event txende; /* COMMUNICATION ERRORS */ task frame_error; begin if(dflags4) $display(“I8251A (%h)at %d: * frame error “,instance_id,$time); status5=1; end
28、 endtask task parity_error;begin 第九章 虚拟器件与虚拟接口模型225if(dflags4) $display(“I8251A (%h) at %d : *parity error data: %b“, instance_id, $time, receivebuf); status3=1; end endtask task overrun_error; begin if(dflags4) $display(“I8251A (%h) at %d: * oerrun error“,instance_id,$time); status4=1; end endtask
29、/* TIMING VIOLATIONS */ integer time_dbus_setup, time_write_begin, time_write_end, time_read_begin, time_read_end, between_write_clks; / to check between write recovery reg reset_signal_in; /to check the reset signal pulse width initial begin time_dbus_setup = -9999; time_write_begin = -9999; time_w
30、rite_end = -9999; time_read_begin = -9999; time_read_end = -9999; between_write_clks = TRV; /start:TRV clk periods since last write end /* Timing analysis for read cycles */ always ( negedge read_) if (chipsel_=0) begin time_read_begin = $time; read_address_watch; 第九章 虚拟器件与虚拟接口模型226end /* Timing vio
31、lation :read pulse must be TRR ns */ always (posedge read_) if (chipsel_=0) begin disable read_address_watch; time_read_end = $time; if(dflags3 end always (negedge reset) 第九章 虚拟器件与虚拟接口模型228begin if(dflags3 / lack of ; disable reset_block; end /* BEHAVIORAL DESCRIPTION */ /* Reset sequence */ initial
32、 begin /power-on reset reset_signal_in=0; - resete; end always resete begin if(dflags5) $display(“I8251A (%h) at %d : performing reset sequence“, instance_id, $time); csel=0; transmitter_reset=1; tdata_out_full=0; tdata_out_wait=0; tdata_hold_full=0; tdata_hold_cts=0; rdatain=0; status=4; /only txe
33、is set txe=1; statusdrv=0; recvdrv=0; txd=1; /line at mark state upon reset until data is transmitted / assign not allowed for status ,etc. rxrdy=0; command=0; dtr_=1; rts_=1; status6=0; / syndat is reset to output low sync_to_transmit=1; /transmit sync char #1 when sync are transmit sync_to_receive
34、=1; between_write_clks = TRV; receive_in_progress=0; disable read_address_watch; disable write_address_watch; 第九章 虚拟器件与虚拟接口模型229disable trans1; disable trans2; disable trans3; disable trans4; disable rcv_blk; disable sync_hunt_blk; disable double_sync_hunt_blk; disable parity_sync_hunt_blk; disable
35、syn_receive_internal; disable asyn_receive; disable break_detect_blk; disable break_delay_blk; end always ( negedge read_) if (chipsel_=0) begin #(TRD) / time for data to show on the data bus if (comdat_=0) /8251A DATA = DATA BUS begin recvdrv=1; rdatain=0; / no receive byte is ready rxrdy=0; status
36、1=0; end else / 8251A STATUS = DATA BUS begin statusdrv=1; if (modreg 1:0 =2b00) / if sync mode status6=0; / reset syndet upon status ready /note: is only reset upon reset or rxd=1 in async mode end end always ( posedge read_) begin #(TDF) /data from read stays on the bus after posedge read_ recvdrv
37、=0; statusdrv=0; end always (negedge write_) begin if(chipsel_=0) status2=0;/transmitter not empty after receiving data status0=0;/transmitter not ready after receiving data end end always (posedge write_) /read the command/data from the CPU if (chipsel_=0) begin if (comdat_=0) /DATA BUS = 8251A DAT
38、A begin case (command0 tdata_hold_full=1; /then mark the data as received and tdata_hold_cts=0; / that it should be sent when cts end 1: / if it is clear to send if(transmitter_reset) / and this is 1st data since reset begin transmitter_reset=0; tdata_out=dbus; tdata_out_wait=1; / then wait for a ne
39、gedge on txc tdata_out_full=1; / and transmit the data tdata_hold_full=0; tdata_hold_cts=0; repeat(TTXRDY) (posedge clk); status0=1; / and set the txrdy status bit end else begin tdata_hold=dbus; / then mark the data as being receive tdata_hold_full=1; / and that it should be transmitted tdata_hold_
40、cts=1; / it becomes not cts, / but do not set the txrdy status bit end endcase end 第九章 虚拟器件与虚拟接口模型231else / DATA BUS = CONTROL begin case (csel) 0: / case 0: MODE INSTRUCTION begin modreg=dbus; if(modreg1:0=0) / synchronous mode begin csel=1; baudmx=1; tstoptotal=0; / no stop bit for synch. Op. end
41、else /synchronous mode begin csel=3; baudmx=1; /1X baud rate if (modreg1:0=2b10) baudmx=16; if(modreg1:0=2b11) baudmx=64; /set up the stop bits in clocks tstoptotal=baudmx; if(modreg7:6=2b10)tstoptotal= tstoptotal + baudmx/2; if(modreg7:6=2b11)tstoptotal= tstoptotal+tstoptotal; end databits=modreg3:
42、2+5; / bits per char data_mask=255 (3-modreg3:2); end 1: /case 1: 1st SYNC CHAR -SYNC MODE begin sync1=dbus; /* the syn. character will be adjusted to the most significant bit to simplify syn, hunt, syncmask is also set to test the top data bits */ case (modreg3:2) 0: begin sync1=sync1 resete; /inte
43、rnal reset if(modreg1:0=0 / disasble the sync receiver disable syn_receive_external; receivebuf=8hff; / reset receive buffer 1s - start_receiver_e; / restart sync mode receiver end if(receive_in_progress=0) - start_receiver_e; repeat(TTXRDY) (posedge clk); status0=1; end endcase end end reg 7:0 seri
44、al_data; reg parity_bit; always wait (tdata_out_full=1) begin :trans1 if(dflags1) $display(“I8251A (%h) at %d: transmitting data: %b“, instance_id,$time, tdata_out); if(tdata_out_wait) / if the data arrived any old time (negedge txc_); / wait for a negedge on txc_ / but if a stop bit was just sent /
45、 do not wait serial_data=tdata_out; 第九章 虚拟器件与虚拟接口模型234if (tstoptotal != 0) / if async mode . begin txd=0; /then send a start bit 1st repeat(baudmx) (negedge txc_); end repeat(databits) /send all start,databits begin txd=serial_data0; repeat(baudmx) (negedge txc_); serial_data=serial_data1; end if (modreg 4) / if parity is enabled .begin parity_bit=(tdata_out if(modreg5=0) parity_bit
