1、Advanced Example,FPGA design techniques for a FIR filter,Outline,constant coefficient FIR filter IP based design flow optimization for speed,area,power EDA tools for the compilation process analysis and synthesis,数字滤波器,可以理解为是一个计算程序或算法，将代表输入信号的数字时间序列转化为代表输出信号的数字时间序列，并在转化过程中，使信号按预定的形式变化。数字滤波器有多种分类，根据数
2、字滤波器冲激响应的时域特征，可将数字滤波器分为两种，即无限长冲激响应（IIR）滤波器和有限长冲激响应（FIR）滤波器。 数字滤波器的功能是将一组输入的数字序列通过一定的运算后转变为另一组输出的数字序列，输入信号与系统函数通过线性卷积产生滤波输出。,数字滤波器可以用差分方程来表示，即数字滤波器的功能是将一组输入的数字序列通过一定的运算后转变为另一组输出的数字序列，输入信号与系统函数通过线性卷积产生滤波输出。 数字滤波器可以用差分方程来表示，即用单位脉冲响应hn可以表示线性时不变离散系统，这时可以用卷积表示上式，如下：,线性时不变(LinearTime-Invariant，LTI)滤波器一般分为有
3、限脉冲响应(Finite Impulse Response，FIR)滤波器和无限脉冲响应(Infinite Impulse Response，IIR)滤波器两类。 FIR数字滤波器是一种非递归系统，其单位冲击响应是有限长序列，即其卷积过程是在有限个采样值中进行的。它的设计问题实质上是确定能满足所要求的转移序列或脉冲响应的常数问题，设计方法主要有窗函数法、频率采样法和等波纹最佳逼近法等。,带有常系数的FIR滤波器是一种线性时不变数字滤波器，其差分方程描述如下：,FIR系统的基本结构,有很多种，大致如下： (1) 直接型 (2) 级联型 (3) 快速卷积型 (4) 线性相位 (5) 频率取样型 这
4、些滤波器在实现结构上彼此之间有着较为紧密的继承和发展关系，而硬件实现方法没有本质上的差异，掌握一种滤波器的FPGA设计方法，只要理清其它类型滤波器的结构，就能很容易快速实现。,Seven-Tap Symmetrical FIR Filter,Six-Tap Symmetrical FIR Filter,直接型FIR滤波器结构图,实例,如上图所示的FIR滤波器，其中输入数据xn为宽度可以调节的有符号数，滤波器长度为5；系数为可以调节宽度的有符号数。yn=C0xn+C1xn-1+C2xn-2+C3xn-3+C4xn-4 如图所示，为该滤波器具体实现时的结构，每一级的乘法或者加法都是并行的，而每一级
5、之间都用寄存器予以隔离，使得每一级之间都是流水的，这种结构同时利用了并行和流水的思路，能够提高数据的吞吐率和滤波器的工作频率,分析,输入采样值x_in为8位有符号数，即数据在-128，127的范围内取值；系数C0，C1，C2，C3，C4同样为8位有符号数，在-128，127的范围内取值，此处波形对应的系数分别为1，-2，4，-2，1；实现的功能可用差分方程描述如下： yn=1xn+(-2)xn-1+4xn-2+(-2)xn-3+1xn-4 当依次输入数据为，-1，-16，-36，-80.，输出对应为：-1，-14，-8，-70，167，-405； 差分方程中xn，xn-1，xn-2，xn-3，
6、xn-4对应x0，x1，x2，x3，x4;以第1个输出为例，此时，差分方程中xn-1，xn-2，xn-3，xn-4均为0，只有xn=-1;故易得第1个输出为-1；,FIR IP, Create a New Quartus II Project Launch IP Toolbench Step 1: Parameterize Step 2: Set Up Simulation Step 3: Generate,Design for speed,流水 组合逻辑平衡 赋值高扇出节点 状态机优化 模块边界输入输出寄存,Defaulted,195.35 MHz ( period = 5.119 ns )
7、 And resources see the report for detail,settings,New frequency,208.99 MHz ( period = 4.785 ns )跟设计、器件本身等诸多因素相关。 此处速度提高 资源？,Design for other targets,面积（area） resource sharing 功耗(power) ,Methods,analysis,Report - Timing Analyzer list paths -locate in last compilation floorplan -list path -Info:,Consi
8、derations,EDA tools quartus DSE(design space explorer) synplify Fundamentally operation principle of FPGA, specific algorithms and architecture ,Homework,Design for area. EDA tools setting principles book to read Advanced FPGA Design: Architecture, Implementation, and Optimization Steve Kilts,Advanc
9、ed FPGA Design: Architecture, Implementation, and Optimization,Product Description This book provides the advanced issues of FPGA design as the underlying theme of the work. In practice, an engineer typically needs to be mentored for several years before these principles are appropriately utilized.
10、The topics that will be discussed in this book are essential to designing FPGAs beyond moderate complexity. The goal of the book is to present practical design techniques that are otherwise only available through mentorship and real-world experience.,Preface xiii Acknowledgments xv 1. Architecting S
11、peed 1 1.1 High Throughput 2 1.2 Low Latency 4 1.3 Timing 6 1.3.1 Add Register Layers 6 1.3.2 Parallel Structures 8 1.3.3 Flatten Logic Structures 10 1.3.4 Register Balancing 12 1.3.5 Reorder Paths 14 1.4 Summary of Key Points 16 2. Architecting Area 17 2.1 Rolling Up the Pipeline 18 2.2 Control-Bas
12、ed Logic Reuse 20 2.3 Resource Sharing 23 2.4 Impact of Reset on Area 25 2.4.1 Resources Without Reset 25 2.4.2 Resources Without Set 26 2.4.3 Resources Without Asynchronous Reset 27 2.4.4 Resetting RAM 29 2.4.5 Utilizing Set/Reset Flip-Flop Pins 31 2.5 Summary of Key Points 34,3. Architecting Power
13、 37 3.1 Clock Control 38 3.1.1 Clock Skew 39 3.1.2 Managing Skew 40 3.2 Input Control 42 3.3 Reducing the Voltage Supply 44 3.4 Dual-Edge Triggered Flip-Flops 44 3.5 Modifying Terminations 45 3.6 Summary of Key Points 46 4. Example Design: The Advanced Encryption Standard 47 4.1 AES Architectures 47
14、 4.1.1 One Stage for Sub-bytes 51 4.1.2 Zero Stages for Shift Rows 51 4.1.3 Two Pipeline Stages for Mix-Column 52 4.1.4 One Stage for Add Round Key 52 4.1.5 Compact Architecture 53 4.1.6 Partially Pipelined Architecture 57 4.1.7 Fully Pipelined Architecture 60 4.2 Performance Versus Area 66 4.3 Othe
15、r Optimizations 67 5. High-Level Design 69 5.1 Abstract Design Techniques 69 5.2 Graphical State Machines 70 5.3 DSP Design 75 5.4 Software/Hardware Codesign 80 5.5 Summary of Key Points 81,6. Clock Domains 83 6.1 Crossing Clock Domains 84 6.1.1 Metastability 86 6.1.2 Solution 1: Phase Control 88 6.1.3 Solution 2: Double Flopping 89 6.1.4 Solution 3: FIFO Structure 92 6.1.5 Partitioning Synchronizer Blocks 97 6.2 Gated Clocks in ASIC Prototypes 97 6.2.1 Clocks Module 98 6.2.2 Gating Removal 99 6.3 Summary of Key Points 100,End,Thanks everyone!,
