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信号完整性分析及设计-高速电路设计.pdf

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1、1信号完整性分析及设计2课程安排 Parts 1: 信号完整性分析概述 Parts 2: 电源完整性分析 Parts 3: 高速电路设计分析技术 Parts 4: 高速 PCB设计与仿真分析3信号完整性分析概述 1: 高速设计简介 2: 信号质量 3:传输线理论和传输线模型- 反射- 串扰- 码间干扰 (ISI)- SSN 4:器件 模型- 晶体管级模型- IBIS模型 5: 管理信号质量- 端接方案- 拓扑结构4高速设计简介 What is Signal Integrity? 什么是信号完整性 ? A Circuit Example一个电路实例 Purpose of SI信号完整性研究的目的

2、56什么是信号完整性 (I)Dr. Howard Johnson: “Maximize the performance and minimize the cost of interconnection technology used in high-speed digital designs”在高速数字设计中把互联结构的性能最大化 ,费用最小化“Signal integrity is a field of study half-way between digital design and analog circuit theory. ”信号完整性涉及到数字和模拟电路理论From http:/7

3、什么是信号完整性 (II) An Engineering Practice 从工程学的角度来看 ,head2right That ensures all signals transmitted are received correctly. 确保正确接收所传输的所有信号head2right That ensures signals do not interfere with one another in a way to degrade reception. 确保信号之间不会相互干扰而损失接收信号的质量head2right That ensures signals do not damage

4、any device. 确保信号不会损害任何电器元件head2right That ensures signals do not pollute the electromagnetic spectrum. 确保信号不会污染电磁频谱890%10%Rise Time Propagation Delay( )46 *确定高速设计 Whenever the drivers rise/fall time is less than 46 times the nets electrical length, the net will tend to behave as a high speed (distri

5、buted) network. 当信号边沿时间小于 4到 6倍的走线传输时延时 , 信号当作高速信号处理 (分布参数模型 )9集总参数和分布参数 All pins sees the same waveform at the same time. 同一时间所有管脚波形相同Different pins see waveforms at different times. The waveforms may or may not be different in shape. 同一时间管脚上波形并不相同LumpedDistributed10These two driver waveforms have

6、the same period, yet the upper signal will create more high speed design problems.i i , i l ill i i l .10 nS = 100 MHz实际考虑点 Rise/fall delay, not data/clock speed, determines the degree to which high speed problems will occur. 是边沿速率而不是信号速率决定是否需要考虑高速信号问题11为什么是边沿速率 ? Edge rates drive several critical f

7、actors 边沿斜率决定下列因素 : Transmission line behavior 传输线行为 The ratio of edge rate to electrical net length determines whether the net behaves as a lumped or distributed system是边沿速率和传输时延决定是否传输行为是集总还是分布参数系统 Power/ground plane bounce 电源地平面波动 Faster switching requires more power in less time, which draws more

8、 power from the power and ground planes快速边沿跳变需要更短时间提供更多能量 Crosstalk 串扰 Faster switching increases the magnetic fields that cause crosstalk 快速边沿跳变增大感应场造成串扰 EMI 电磁干扰 Stronger magnetic fields mean more energy is radiated强的感应场意味着更多的辐射案例 : 2M时钟问题12脉冲频谱思考 : 理想脉冲的频谱13T1/d 1/trdtr频率 (对数 )-20dB/dec-40dB/decA

9、V( or I) = 2A(d+tr)/TV( or I) = 0.64A/TfV( or I) = 0.2A/Ttrf2特性思考 : 信号带宽 , 分贝频率 , Fknee 的概念和应用14频域到时域思考 : 信号的衰减与畸变15SI Perspectives 信号完整性的研究范围 On Silicon (Silicon Level) SI/PI 芯片 On PKG (Package Level) SI/PI 封装 Chip to Chip (Board Level) SI/PI 板级16Board Level SI Perspectives 板级信号完整性的研究范围17一个电路实例 (有和

10、没有 Stub)w/ or w/o Stub18square6 Stub Possible Locations 可能的可能的可能的可能的 Stub位置位置位置位置square6Routing stubs 走线的走线的走线的走线的 Stubsquare6Plating stubs in PKG 封装中的封装中的封装中的封装中的 Plating bar造成造成造成造成square6Through hole via stubs 通孔造成通孔造成通孔造成通孔造成一个电路实例 (有和没有 Stub)19信号完整性工程师的作用 elipsisInput OutputOutputInputcircle4 T

11、he job of the board level SI engineer is to design the interconnect from chip to chip such that the waveform at the receiver is “good” enough to be detected. 设计互连系统保证信号接收的质量和正确性20信号质量square4 What is Signal Quality ? 什么是信号质量 ?square4 Signal Quality Metrics 描述信号质量的参数21square6 Designer has been trying

12、to Maintain the Characteristics of a Signal at the Driver Output, all the way through the Interconnects and especially on the Receiver Input. 设计者必须保证设计者必须保证设计者必须保证设计者必须保证信号在驱动端信号在驱动端信号在驱动端信号在驱动端 , 互连结构上互连结构上互连结构上互连结构上 , 特别是接收端上的特性特别是接收端上的特性特别是接收端上的特性特别是接收端上的特性square6 The ideal situation is To Receiv

13、e the Signal in Same Form as Generated and Driven by the Driver. (One exception is series termination case, the driver side signal looks ugly, but signal in the receiver side is pretty good.) 理想情理想情理想情理想情况是接收端波形与驱动端波形一致况是接收端波形与驱动端波形一致况是接收端波形与驱动端波形一致况是接收端波形与驱动端波形一致 (串联匹配是一个串联匹配是一个串联匹配是一个串联匹配是一个例外情况例外

14、情况例外情况例外情况 , 驱动端波形看起来很不规则驱动端波形看起来很不规则驱动端波形看起来很不规则驱动端波形看起来很不规则 , 接收端波形接收端波形接收端波形接收端波形却很好却很好却很好却很好 )什么是信号质量22信号质量定义square6 Overshoot, Undershoot (or Overshoot High, Overshoot Low) 上冲 ,下冲square6 Ringback High, Ringback Low 回冲square6 Ringing 振铃square6 Monotonicity and Non-monotonicity 单调性和非单调性square6 Ji

15、tter 抖动23Non-monotonicityRingingRinging信号质量定义 (继续 )24square6 Overshoot, Undershoot 上冲上冲上冲上冲 ,下冲下冲下冲下冲circle6 Overshoot is the Maximum Voltage by Which a Signal Extends Above Vcc; Undershoot is the Maximum Voltage by Which a Signal Extends Below Vss. 上冲是信号高于 Vcc的 最高电压 , 下冲是信号低于 Vss的最低电压circle6 Too Mu

16、ch May Cause Problems at Receivers, by Dissipating Excessive Energy at Receiver or even damage the devices in the channel. 过大会造成过多能量以及损坏器件square6Ringback 回冲回冲回冲回冲circle6 Ringback is the Amount a Signal Returns Above Vss or Below Vcc Immediately After an Undershoot or Overshoot.回冲是信号在达到最低电压或最高电压后回到 V

17、ss之上或 Vcc之下的电压circle6 Too Much Can Cause Logic Violation, Leading to Functional Failure. 过大会造成逻辑错误circle6 Ringback Voltage Levels Must Be Controlled to Remainwithin SwitchingThreshold Regions. 回冲必须控制在保证翻转门限电平的范围信号质量定义 (继续 )25square6 Ringing 振铃振铃振铃振铃circle6 Ringing is Defined As Oscillations at the E

18、nd of A Signal Transition. 振铃定义为信号跳变之后的振荡circle6 Too Much Ringing Can Lead to Logical Malfunctions. 过大会造成逻辑错误square6 Monotonicity 单调性单调性单调性单调性circle6 Glitch on a Rising Or Falling Waveform. 上升或下降沿的毛刺circle6 Non-Monotonic Waveform Around Switching Thresholds Can Lead To Logical Malfunctions. 波形在翻转门限电

19、平处的非单调可能造成逻辑判断错误 (特别是对时钟 )信号质量定义 (继续 )26square6 Glitch 毛刺毛刺毛刺毛刺circle6Noise That Looks Like A Single Pulse 像单个脉冲一样的噪声circle6 Glitch Reaching Switching Thresholds Can Lead To Logical Malfunctions 达到翻转电平门限的毛刺可能造成逻辑错误信号质量定义 (继续 )27square6 Skew 偏移偏移偏移偏移circle6 Signal Skew Is The Time Difference Between

20、Signals in A Group Arriving at Their Destinations (ex: Unmatched Branches Length,Unmatched Loads) 信号偏移定义为一组信号之间的时间偏差circle6 Skew Can Be Caused by Reflections and Crosstalk 可能由反射和串扰造成circle6 Skew Between Signals Can Lead to Logical Malfunctions 可能造成逻辑错误信号质量定义 (继续 )28square6 Rising and Falling Time 上升

21、下降时间上升下降时间上升下降时间上升下降时间circle6 Time between 20% and 80% Points of The Rise and Fall Timeof A Signal Respectively 上升下降沿电压在 20%和 80%之间的时间circle6 Rise and Fall Times of A Signal at Receiver Inputs Must MeetReceiver Specifications. 必须满足接收器件的触发要求信号质量定义 (继续 )29square6 “High” and “Low” Times 高低电平时间高低电平时间高低电

22、平时间高低电平时间circle6 High Time of A Signal is The Time The Signal is Considered at“High Logic Level” and Low Time of A Signal is The Time TheSignal is Considered at “Low Logic Level” 信号保证为高或低电平的时间circle6 At Receiver Inputs, Signal High and Low Times Must MeetReceiver Specifications 必须满足接收器件的时序要求信号质量定义 (

23、继续 )30square6 ITU-T Definition for Jitter 抖动定义抖动定义抖动定义抖动定义circle6Jitter is the short term variation of the significant instants of a digital signal from their ideal positions in time. 输出跃迁与其理想位置的偏差8Bell Communications Research, Inc (Bellcore), “Synchrouous Optical Network (SONET) Transport Systems: Common Generic Criteria, TR-253-CORE”, Issue 2, Rev No. 1, December 1997信号质量定义 (继续 )

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