1、汉字点阵显示 VHDL 源程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity hzxs isport(clk1,clk2:in std_logic;rd:out std_logic;we: out std_logic;ledw:out std_logic_vector(2 downto 0);d:out std_logic_vector(0 downto 7);end hzxs;architecture hav of hzxs
2、 issignal count:std_logic_vector(0 to 2);signal a: std_logic_vector(3 downto 0);begin process(clk2)beginif clk2event and clk2=1 thencountdddddddddddddddddananananan=0;bn=0;cn=0;dn=0;end case;elsif clr=0 thenan=0;bn=0;cn=0;dn=0;end if;end process;end hav;2）计分器 JFQlibrary ieee;use ieee.std_logic_1164.
3、all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity jfq isport(en1:in std_logic;clk3:in std_logic;bs:out std_logic_vector(3 downto 0);ss:out std_logic_vector(3 downto 0); gs:out std_logic_vector(3 downto 0);add:in std_logic;dec:in std_logic);end jfq;architecture hav of jfq isbegi
4、nprocess(clk3,en1,add,dec)variable ssw:std_logic_vector(3 downto 0);variable bsw:std_logic_vector(3 downto 0);beginbsw:=“0001“;if clk3=1 and clk3event thenif en1=1 thenif add=1 thenif ssw=“1001“ thenbsw:=bsw+1;ssw:=“0000“;elsessw:=ssw+1;end if;elsif dec=1 thenif ssw=“1111“ thenbsw:=bsw-1;ssw:=“1001“
5、;elsessw:=ssw-1;end if;end if;end if;end if;ss=ssw;bs=bsw;gs=“0000“;end process;end hav;3) 选择器 XZQlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity xzq isport( a1,b1:in std_logic;abw:in std_logic_vector(0 to 3);asw:in std_logic_vector(0 to 3
6、); agw:in std_logic_vector(0 to 3);bbw:in std_logic_vector(0 to 3);bsw:in std_logic_vector(0 to 3); bgw:in std_logic_vector(0 to 3);obw:out std_logic_vector(0 to 3);osw:out std_logic_vector(0 to 3); ogw:out std_logic_vector(0 to 3);end xzq;architecture hav of xzq isbeginprocess(a1,b1)beginif a1=1 an
7、d b1=0 thenobw=abw;osw=asw;ogw=agw;elsif a1=0 and b1=1 thenobw=bbw;osw=bsw;ogw=bgw;end if;end process;end hav;4）译码器 YMQlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity ymq isport( clk2:in std_logic;bw:in std_logic_vector(3 downto 0);sw:in s
8、td_logic_vector(3 downto 0); gw:in std_logic_vector(3 downto 0);y:out std_logic_vector(7 downto 0);ledw:out std_logic_vector(2 downto 0);end ymq;architecture hav of ymq issignal knum:std_logic_vector(3 downto 0);signal count:std_logic_vector(2 downto 0);beginprocess(clk2)beginif clk2event and clk2=1
9、 thenif count2 thencount=count+1;elsecount=“000“;end if;end if;end process;ledw=count;knum=gw when count=0 elsesw when count=1 elsebw when count=2 ;y=“00111111“ when knum=“0000“ else“00000110“ when knum=“0001“ else“01011011“ when knum=“0010“ else“01001111“ when knum=“0011“ else“01100110“ when knum=“0100“ else“01101101“ when knum=“0101“ else“01111101“ when knum=“0110“ else“00000111“ when knum=“0111“ else“01111111“ when knum=“1000“ else“01101111“ when knum=“1001“ else“00000000“ ;end hav;
