1、附录 DE2-115 实验板引脚配置信息 DE2-115开发板：目标芯片 Cyclone IV E EP4CE115F29C7；存储器64MB x2 SDRAM、2MB SRAM、8MB Flash；通信端口：10/100/1000 以太网口 x2、USB 2.0 时钟：50MHz x3 振荡器、SMA in/out Altera 配置芯片 EPCS64表 1 拨动开关引脚配置Signal Name FPGA Pin No. Description I/O StandardSW0 PIN_AB28 Slide Switch0 Depending on JP7SW1 PIN_AC28 Slide
2、 Switch1 Depending on JP7SW2 PIN_AC27 Slide Switch2 Depending on JP7SW3 PIN_AD27 Slide Switch3 Depending on JP7SW4 PIN_AB27 Slide Switch4 Depending on JP7SW5 PIN_AC26 Slide Switch5 Depending on JP7SW6 PIN_AD26 Slide Switch6 Depending on JP7SW7 PIN_AB26 Slide Switch7 Depending on JP7SW8 PIN_AC25 Slid
3、e Switch8 Depending on JP7SW9 PIN_AB25 Slide Switch9 Depending on JP7SW10 PIN_AC24 Slide Switch10 Depending on JP7SW11 PIN_AB24 Slide Switch11 Depending on JP7SW12 PIN_AB23 Slide Switch12 Depending on JP7SW13 PIN_AA24 Slide Switch13 Depending on JP7SW14 PIN_AA23 Slide Switch14 Depending on JP7SW15 P
4、IN_AA22 Slide Switch15 Depending on JP7SW16 PIN_Y24 Slide Switch16 Depending on JP7SW17 PIN_Y23 Slide Switch17 Depending on JP7表 2 按钮开关引脚配置Signal Name FPGA Pin No. Description I/O StandardKEY0 PIN_M23 Push-button0 Depending on JP7KEY1 PIN_M21 Push-button1 Depending on JP7KEY2 PIN_N21 Push-button2 De
5、pending on JP7KEY3 PIN_R24 Push-button3 Depending on JP7表 3 LED 引脚配置Signal Name FPGA Pin No. Description I/OStandardLEDR0 PIN_G19 LED Red0 2.5VLEDR1 PIN_F19 LED Red1 2.5VLEDR2 PIN_E19 LED Red2 2.5VLEDR3 PIN_F21 LED Red3 2.5VLEDR4 PIN_F18 LED Red4 2.5VLEDR5 PIN_E18 LED Red5 2.5VLEDR6 PIN_J19 LED Red6
6、 2.5VLEDR7 PIN_H19 LED Red7 2.5VLEDR8 PIN_J17 LED Red8 2.5VLEDR9 PIN_G17 LED Red9 2.5VLEDR10 PIN_J15 LED Red10 2.5VLEDR11 PIN_H16 LED Red11 2.5VLEDR12 PIN_J16 LED Red12 2.5VLEDR13 PIN_H17 LED Red13 2.5VLEDR14 PIN_F15 LED Red14 2.5VLEDR15 PIN_G15 LED Red15 2.5VLEDR16 PIN_G16 LED Red16 2.5VLEDR17 PIN_
7、H15 LED Red17 2.5VLEDG0 PIN_E21 LED Green0 2.5VLEDG1 PIN_E22 LED Green1 2.5VLEDG2 PIN_E25 LED Green2 2.5VLEDG3 PIN_E24 LED Green3 2.5VLEDG4 PIN_H21 LED Green4 2.5VLEDG5 PIN_G20 LED Green5 2.5VLEDG6 PIN_G22 LED Green6 2.5VLEDG7 PIN_G21 LED Green7 2.5VLEDG8 PIN_F17 LED Green8 2.5V表 4 七段数码管引脚配置Signal N
8、ame FPGA Pin No. Description I/O StandardHEX00 PIN_G18 Seven Segment Digit 00 2.5VHEX01 PIN_F22 Seven Segment Digit 01 2.5VHEX02 PIN_E17 Seven Segment Digit 02 2.5VHEX03 PIN_L26 Seven Segment Digit 03 Depending on JP7HEX04 PIN_L25 Seven Segment Digit 04 Depending on JP7HEX05 PIN_J22 Seven Segment Di
9、git 05 Depending on JP7HEX06 PIN_H22 Seven Segment Digit 06 Depending on JP7HEX10 PIN_M24 Seven Segment Digit 10 Depending on JP7HEX11 PIN_Y22 Seven Segment Digit 11 Depending on JP7HEX12 PIN_W21 Seven Segment Digit 12 Depending on JP7HEX13 PIN_W22 Seven Segment Digit 13 Depending on JP7HEX14 PIN_W2
10、5 Seven Segment Digit 14 Depending on JP7HEX15 PIN_U23 Seven Segment Digit 15 Depending on JP7HEX16 PIN_U24 Seven Segment Digit 16 Depending on JP7HEX20 PIN_AA25 Seven Segment Digit 20 Depending on JP7HEX21 PIN_AA26 Seven Segment Digit 21 Depending on JP7HEX22 PIN_Y25 Seven Segment Digit 22 Dependin
11、g on JP7HEX23 PIN_W26 Seven Segment Digit 23 Depending on JP7HEX24 PIN_Y26 Seven Segment Digit 24 Depending on JP7HEX25 PIN_W27 Seven Segment Digit 25 Depending on JP7HEX26 PIN_W28 Seven Segment Digit 26 Depending on JP7HEX30 PIN_V21 Seven Segment Digit 30 Depending on JP7HEX31 PIN_U21 Seven Segment
12、 Digit 31 Depending on JP7HEX32 PIN_AB20 Seven Segment Digit 32 Depending on JP6HEX33 PIN_AA21 Seven Segment Digit 33 Depending on JP6HEX34 PIN_AD24 Seven Segment Digit 34 Depending on JP6HEX35 PIN_AF23 Seven Segment Digit 35 Depending on JP6HEX36 PIN_Y19 Seven Segment Digit 36 Depending on JP6HEX40
13、 PIN_AB19 Seven Segment Digit 40 Depending on JP6HEX41 PIN_AA19 Seven Segment Digit 41 Depending on JP6HEX42 PIN_AG21 Seven Segment Digit 42 Depending on JP6HEX43 PIN_AH21 Seven Segment Digit 43 Depending on JP6HEX44 PIN_AE19 Seven Segment Digit 44 Depending on JP6HEX45 PIN_AF19 Seven Segment Digit
14、45 Depending on JP6HEX46 PIN_AE18 Seven Segment Digit 46 Depending on JP6HEX50 PIN_AD18 Seven Segment Digit 50 Depending on JP6HEX51 PIN_AC18 Seven Segment Digit 51 Depending on JP6HEX52 PIN_AB18 Seven Segment Digit 52 Depending on JP6HEX53 PIN_AH19 Seven Segment Digit 53 Depending on JP6HEX54 PIN_A
15、G19 Seven Segment Digit 54 Depending on JP6HEX55 PIN_AF18 Seven Segment Digit 55 Depending on JP6HEX56 PIN_AH18 Seven Segment Digit 56 Depending on JP6HEX60 PIN_AA17 Seven Segment Digit 60 Depending on JP6HEX61 PIN_AB16 Seven Segment Digit 61 Depending on JP6HEX62 PIN_AA16 Seven Segment Digit 62 Dep
16、ending on JP6HEX63 PIN_AB17 Seven Segment Digit 63 Depending on JP6HEX64 PIN_AB15 Seven Segment Digit 64 Depending on JP6HEX65 PIN_AA15 Seven Segment Digit 65 Depending on JP6HEX66 PIN_AC17 Seven Segment Digit 66 Depending on JP6HEX70 PIN_AD17 Seven Segment Digit 70 Depending on JP6HEX71 PIN_AE17 Se
17、ven Segment Digit 71 Depending on JP6HEX72 PIN_AG17 Seven Segment Digit 72 Depending on JP6HEX73 PIN_AH17 Seven Segment Digit 73 Depending on JP6HEX74 PIN_AF17 Seven Segment Digit 74 Depending on JP6HEX75 PIN_AG18 Seven Segment Digit 75 Depending on JP6HEX76 PIN_AA14 Seven Segment Digit 76 3.3V表 5 时
18、钟信号引脚配置信息Signal Name FPGA Pin No. Description I/O StandardCLOCK_50 PIN_Y2 50 MHz clock input 3.3VCLOCK2_50 PIN_AG14 50 MHz clock input 3.3VCLOCK3_50 PIN_AG15 50 MHz clock input Depending on JP6SMA_CLKOUT PIN_AE23 External (SMA) clock output Depending on JP6SMA_CLKIN PIN_AH14 External (SMA) clock inp
19、ut 3.3V表 6 LCD 模块引脚配置Signal Name FPGAPinNo. Description I/OLCD_DATA7 PIN_M5 LCD Data7 StandardLCD_DATA6 PIN_M3 LCD Data6 3.3VLCD_DATA5 PIN_K2 LCD Data5 3.3VLCD_DATA4 PIN_K1 LCD Data4 3.3VLCD_DATA3 PIN_K7 LCD Data3 3.3VLCD_DATA2 PIN_L2 LCD Data2 3.3VLCD_DATA1 PIN_L1 LCD Data1 3.3VLCD_DATA0 PIN_L3 LCD
20、 Data0 3.3VLCD_EN PIN_L4 LCD Enable 3.3VLCD_RW PIN_M1 LCD Read/Write Select, 0 = Write, 1 = Read 3.3VLCD_RS PIN_M2 LCD Command/Data Select, 0 = Command, 1 = Data 3.3VLCD_ON PIN_L5 LCD Power ON/OFF 3.3VLCD_BLON PIN_L6 LCD Back Light ON/OFF 3.3V表 7 HSMC 接口引脚配置Signal Name FPGA Pin No. Description I/O S
21、tandardHSMC_CLKIN0 PIN_AH15 Dedicated clock input Depending on JP6HSMC_CLKIN_N1 PIN_J28 LVDS RX or CMOS I/O or differential clock inputDepending on JP7HSMC_CLKIN_N2 PIN_Y28 LVDS RX or CMOS I/O or differential clock inputDepending on JP7HSMC_CLKIN_P1 PIN_J27 LVDS RX or CMOS I/O or differential clock
22、inputDepending on JP7HSMC_CLKIN_P2 PIN_Y27 LVDS RX or CMOS I/O or differential clock inputDepending on JP7HSMC_CLKOUT0 PIN_AD28 Dedicated clock output Depending on JP7HSMC_CLKOUT_N1 PIN_G24 LVDS TX or CMOS I/O or differential clock input/outputDepending on JP7HSMC_CLKOUT_N2 PIN_V24 LVDS TX or CMOS I
23、/O or differential clock input/outputDepending on JP7HSMC_CLKOUT_P1 PIN_G23 LVDS TX or CMOS I/O or differential clock input/outputDepending on JP7HSMC_CLKOUT_P2 PIN_V23 LVDS TX or CMOS I/O or differential clock input/outputDepending on JP7HSMC_D0 PIN_AE26 LVDS TX or CMOS I/O Depending on JP7HSMC_D1
24、PIN_AE28 LVDS TX or CMOS I/O Depending on JP7HSMC_D2 PIN_AE27 LVDS TX or CMOS I/O Depending on JP7HSMC_D3 PIN_AF27 LVDS TX or CMOS I/O Depending on JP7HSMC_RX_D_N0 PIN_F25 LVDS RX bit 0n or CMOS I/O Depending on JP7HSMC_RX_D_N1 PIN_C27 LVDS RX bit 1n or CMOS I/O Depending on JP7HSMC_RX_D_N2 PIN_E26
25、LVDS RX bit 2n or CMOS I/O Depending on JP7HSMC_RX_D_N3 PIN_G26 LVDS RX bit 3n or CMOS I/O Depending on JP7HSMC_RX_D_N4 PIN_H26 LVDS RX bit 4n or CMOS I/O Depending on JP7HSMC_RX_D_N5 PIN_K26 LVDS RX bit 5n or CMOS I/O Depending on JP7HSMC_RX_D_N6 PIN_L24 LVDS RX bit 6n or CMOS I/O Depending on JP7H
26、SMC_RX_D_N7 PIN_M26 LVDS RX bit 7n or CMOS I/O Depending on JP7HSMC_RX_D_N8 PIN_R26 LVDS RX bit 8n or CMOS I/O Depending on JP7HSMC_RX_D_N9 PIN_T26 LVDS RX bit 9n or CMOS I/O Depending on JP7HSMC_RX_D_N10 PIN_U26 LVDS RX bit 10n or CMOS I/O Depending on JP7HSMC_RX_D_N11 PIN_L22 LVDS RX bit 11n or CM
27、OS I/O Depending on JP7HSMC_RX_D_N12 PIN_N26 LVDS RX bit 12n or CMOS I/O Depending on JP7HSMC_RX_D_N13 PIN_P26 LVDS RX bit 13n or CMOS I/O Depending on JP7HSMC_RX_D_N14 PIN_R21 LVDS RX bit 14n or CMOS I/O Depending on JP7HSMC_RX_D_N15 PIN_R23 LVDS RX bit 15n or CMOS I/O Depending on JP7HSMC_RX_D_N16
28、 PIN_T22 LVDS RX bit 16n or CMOS I/O Depending on JP7HSMC_RX_D_P0 PIN_F24 LVDS RX bit 0 or CMOS I/O Depending on JP7HSMC_RX_D_P1 PIN_D26 LVDS RX bit 1 or CMOS I/O Depending on JP7HSMC_RX_D_P2 PIN_F26 LVDS RX bit 2 or CMOS I/O Depending on JP7HSMC_RX_D_P3 PIN_G25 LVDS RX bit 3 or CMOS I/O Depending o
29、n JP7HSMC_RX_D_P4 PIN_H25 LVDS RX bit 4 or CMOS I/O Depending on JP7HSMC_RX_D_P5 PIN_K25 LVDS RX bit 5 or CMOS I/O Depending on JP7HSMC_RX_D_P6 PIN_L23 LVDS RX bit 6 or CMOS I/O Depending on JP7HSMC_RX_D_P7 PIN_M25 LVDS RX bit 7 or CMOS I/O Depending on JP7HSMC_RX_D_P8 PIN_R25 LVDS RX bit 8 or CMOS
30、I/O Depending on JP7HSMC_RX_D_P9 PIN_T25 LVDS RX bit 9 or CMOS I/O Depending on JP7HSMC_RX_D_P10 PIN_U25 LVDS RX bit 10 or CMOS I/O Depending on JP7HSMC_RX_D_P11 PIN_L21 LVDS RX bit 11 or CMOS I/O Depending on JP7HSMC_RX_D_P12 PIN_N25 LVDS RX bit 12 or CMOS I/O Depending on JP7HSMC_RX_D_P13 PIN_P25
31、LVDS RX bit 13 or CMOS I/O Depending on JP7HSMC_RX_D_P14 PIN_P21 LVDS RX bit 14 or CMOS I/O Depending on JP7HSMC_RX_D_P15 PIN_R22 LVDS RX bit 15 or CMOS I/O Depending on JP7HSMC_RX_D_P16 PIN_T21 LVDS RX bit 16 or CMOS I/O Depending on JP7HSMC_TX_D_N0 PIN_D28 LVDS TX bit 0n or CMOS I/O Depending on J
32、P7HSMC_TX_D_N1 PIN_E28 LVDS TX bit 1n or CMOS I/O Depending on JP7HSMC_TX_D_N2 PIN_F28 LVDS TX bit 2n or CMOS I/O Depending on JP7HSMC_TX_D_N3 PIN_G28 LVDS TX bit 3n or CMOS I/O Depending on JP7HSMC_TX_D_N4 PIN_K28 LVDS TX bit 4n or CMOS I/O Depending on JP7HSMC_TX_D_N5 PIN_M28 LVDS TX bit 5n or CMO
33、S I/O Depending on JP7HSMC_TX_D_N6 PIN_K22 LVDS TX bit 6n or CMOS I/O Depending on JP7HSMC_TX_D_N7 PIN_H24 LVDS TX bit 7n or CMOS I/O Depending on JP7HSMC_TX_D_N8 PIN_J24 LVDS TX bit 8n or CMOS I/O Depending on JP7HSMC_TX_D_N9 PIN_P28 LVDS TX bit 9n or CMOS I/O Depending on JP7HSMC_TX_D_N10 PIN_J26
34、LVDS TX bit 10n or CMOS I/O Depending on JP7HSMC_TX_D_N11 PIN_L28 LVDS TX bit 11n or CMOS I/O Depending on JP7HSMC_TX_D_N12 PIN_V26 LVDS TX bit 12n or CMOS I/O Depending on JP7HSMC_TX_D_N13 PIN_R28 LVDS TX bit 13n or CMOS I/O Depending on JP7HSMC_TX_D_N14 PIN_U28 LVDS TX bit 14n or CMOS I/O Dependin
35、g on JP7HSMC_TX_D_N15 PIN_V28 LVDS TX bit 15n or CMOS I/O Depending on JP7HSMC_TX_D_N16 PIN_V22 LVDS TX bit 16n or CMOS I/O Depending on JP7HSMC_TX_D_P0 PIN_D27 LVDS TX bit 0 or CMOS I/O Depending on JP7HSMC_TX_D_P1 PIN_E27 LVDS TX bit 1 or CMOS I/O Depending on JP7HSMC_TX_D_P2 PIN_F27 LVDS TX bit 2
36、 or CMOS I/O Depending on JP7HSMC_TX_D_P3 PIN_G27 LVDS TX bit 3 or CMOS I/O Depending on JP7HSMC_TX_D_P4 PIN_K27 LVDS TX bit 4 or CMOS I/O Depending on JP7HSMC_TX_D_P5 PIN_M27 LVDS TX bit 5 or CMOS I/O Depending on JP7HSMC_TX_D_P6 PIN_K21 LVDS TX bit 6 or CMOS I/O Depending on JP7HSMC_TX_D_P7 PIN_H2
37、3 LVDS TX bit 7 or CMOS I/O Depending on JP7HSMC_TX_D_P8 PIN_J23 LVDS TX bit 8 or CMOS I/O Depending on JP7HSMC_TX_D_P9 PIN_P27 LVDS TX bit 9 or CMOS I/O Depending on JP7HSMC_TX_D_P10 PIN_J25 LVDS TX bit 10 or CMOS I/O Depending on JP7HSMC_TX_D_P11 PIN_L27 LVDS TX bit 11 or CMOS I/O Depending on JP7
38、HSMC_TX_D_P12 PIN_V25 LVDS TX bit 12 or CMOS I/O Depending on JP7HSMC_TX_D_P13 PIN_R27 LVDS TX bit 13 or CMOS I/O Depending on JP7HSMC_TX_D_P14 PIN_U27 LVDS TX bit 14 or CMOS I/O Depending on JP7HSMC_TX_D_P15 PIN_V27 LVDS TX bit 15 or CMOS I/O Depending on JP7HSMC_TX_D_P16 PIN_U22 LVDS TX bit 16 or
39、CMOS I/O Depending on JP7表 8 GPIO 引脚配置信息 Signal Name FPGA Pin No. Description I/O StandardGPIO0 PIN_AB22 GPIO Connection DATA0 Depending on JP6GPIO1 PIN_AC15 GPIO Connection DATA1 Depending on JP6GPIO2 PIN_AB21 GPIO Connection DATA2 Depending on JP6GPIO3 PIN_Y17 GPIO Connection DATA3 Depending on JP
40、6GPIO4 PIN_AC21 GPIO Connection DATA4 Depending on JP6GPIO5 PIN_Y16 GPIO Connection DATA5 Depending on JP6GPIO6 PIN_AD21 GPIO Connection DATA6 Depending on JP6GPIO7 PIN_AE16 GPIO Connection DATA7 Depending on JP6GPIO8 PIN_AD15 GPIO Connection DATA8 Depending on JP6GPIO9 PIN_AE15 GPIO Connection DATA
41、9 Depending on JP6GPIO10 PIN_AC19 GPIO Connection DATA10 Depending on JP6GPIO11 PIN_AF16 GPIO Connection DATA11 Depending on JP6GPIO12 PIN_AD19 GPIO Connection DATA12 Depending on JP6GPIO13 PIN_AF15 GPIO Connection DATA13 Depending on JP6GPIO14 PIN_AF24 GPIO Connection DATA14 Depending on JP6GPIO15
42、PIN_AE21 GPIO Connection DATA15 Depending on JP6GPIO16 PIN_AF25 GPIO Connection DATA16 Depending on JP6GPIO17 PIN_AC22 GPIO Connection DATA17 Depending on JP6GPIO18 PIN_AE22 GPIO Connection DATA18 Depending on JP6GPIO19 PIN_AF21 GPIO Connection DATA19 Depending on JP6GPIO20 PIN_AF22 GPIO Connection
43、DATA20 Depending on JP6GPIO21 PIN_AD22 GPIO Connection DATA21 Depending on JP6GPIO22 PIN_AG25 GPIO Connection DATA22 Depending on JP6GPIO23 PIN_AD25 GPIO Connection DATA23 Depending on JP6GPIO24 PIN_AH25 GPIO Connection DATA24 Depending on JP6GPIO25 PIN_AE25 GPIO Connection DATA25 Depending on JP6GP
44、IO26 PIN_AG22 GPIO Connection DATA26 Depending on JP6GPIO27 PIN_AE24 GPIO Connection DATA27 Depending on JP6GPIO28 PIN_AH22 GPIO Connection DATA28 Depending on JP6GPIO29 PIN_AF26 GPIO Connection DATA29 Depending on JP6GPIO30 PIN_AE20 GPIO Connection DATA30 Depending on JP6GPIO31 PIN_AG23 GPIO Connec
45、tion DATA31 Depending on JP6GPIO32 PIN_AF20 GPIO Connection DATA32 Depending on JP6GPIO33 PIN_AH26 GPIO Connection DATA33 Depending on JP6GPIO34 PIN_AH23 GPIO Connection DATA34 Depending on JP6GPIO35 PIN_AG26 GPIO Connection DATA35 Depending on JP6表 9 扩展接口引脚配置信息 Signal Name FPGA Pin No. Description
46、I/O StandardEX_IO0 PIN_J10 Extended IO0 3.3VEX_IO1 PIN_J14 Extended IO1 3.3VEX_IO2 PIN_H13 Extended IO2 3.3VEX_IO3 PIN_H14 Extended IO3 3.3VEX_IO4 PIN_F14 Extended IO4 3.3VEX_IO5 PIN_E10 Extended IO5 3.3VEX_IO6 PIN_D9 Extended IO6 3.3V表 10 ADV7123 引脚配置Signal Name FPGA Pin No. Description I/O Standar
47、dVGA_R0 PIN_E12 VGA Red0 3.3VVGA_R1 PIN_E11 VGA Red1 3.3VVGA_R2 PIN_D10 VGA Red2 3.3VVGA_R3 PIN_F12 VGA Red3 3.3VVGA_R4 PIN_G10 VGA Red4 3.3VVGA_R5 PIN_J12 VGA Red5 3.3VVGA_R6 PIN_H8 VGA Red6 3.3VVGA_R7 PIN_H10 VGA Red7 3.3VVGA_G0 PIN_G8 VGA Green0 3.3VVGA_G1 PIN_G11 VGA Green1 3.3VVGA_G2 PIN_F8 VGA Green2 3.3VVGA_G3 PIN_H12 VGA Green3 3.3VVGA_G4 PIN_C8 VGA Green
