1、 1AN-978 RevD Application Note AN-978 HV Floating MOS-Gate Driver ICs (HEXFET is a trademark of International Rectifier) Table of Contents Page Gate drive requirement of high-side devices. 2 A typical block diagram . 3 How to select the bootstrap components 5 How to calculate the power dissipation
2、in an MGD. 6 How to deal with negative transients on the Vspin . 9 Layout and other general guidelines. 11 How to boost gate drive current to drive modules. 14 How to provide a continuous gate drive 17 How to generate a negative gate bias. 19 How to drive a buck converter. 22 Dual forward converter
3、and switched reluctance motor drives . 24 Full bridge with current mode control 24 Brushless and induction motor drives . 26 Push-pull . 27 High-side P-channel 27 Troubleshooting guidelines . 28 2AN-978 RevD 1. GATE DRIVE REQUIREMENTS OF HIGH-SIDE DEVICES The gate drive requirements for a power MOS
4、FET or IGBT utilized as a high-side switch (the drain is connected to the high voltage rail, as shown in Figure 1) driven in full enhancement (i.e., lowest voltage drop across its terminals) can be summarized as follows: 1. Gate voltage must be 10 V to 15 V higher than the source voltage. Being a hi
5、gh-side switch, such gate voltage would have to be higher than the rail voltage, which is frequently the highest voltage available in the system. 2. The gate voltage must be controllable from the logic, which is normally referenced to ground. Thus, the control signals have to be level-shifted to the
6、 source of the high-side power device, which, in most applications, swings between the two rails. 3. The power absorbed by the gate drive circuitry should not significantly affect the overall efficiency. Figure 1: Power MOSFET in the High-Side Configuration With these constraints in mind, several te
7、chniques are presently used to perform this function, as shown in principle in Table I (see pg. 29). Each basic circuit can be implemented in a wide variety of configurations. International Rectifiers family of MOS-gate drivers (MGDs) integrate most of the functions required to drive one high-side a
8、nd one low-side power MOSFET or IGBT in a compact, high performance package. With the addition of few components, they provide very fast switching speeds, as shown in Table II (see pg. 30) for the IRS2110, and low power dissipation. They can operate on the bootstrap principle or with a floating powe
9、r supply. Used in the bootstrap mode, they can operate in most applications from frequencies in the tens of Hz up to hundreds of kHz. GATESOURCEV+HIGH VOLTAGE RAIL 3AN-978 RevD 2. TYPICAL BLOCK DIAGRAM The block diagram of the IRS2110 will be used to illustrate the typical structure of most MGDs; th
10、is is shown in Figure 2. It comprises a drive circuit for a ground referenced power transistor, another for a high-side one, level translators and input logic circuitry . Figure 2: Block Diagram of the IRS2110 Figure 3: Silicon Cross-Section Showing the Parasitic Capacitances VDD H IN SDL IN V SS R
11、S R S VDD/ VCCLEVELTRANSLATORAND PWDISCRIMINATORPULSEGENERATORUVDETECTDELAYVDD/ VBSLEVELTRANSLATORPULSEDISCRIMINATORCd-subCb-subUVDETECTLATCHLOGICQQVBHO VSLO2COMMCBOOTV CC V R VDD/ VCCLEVELTRANSLATORAND PWDISCRIMINATORHIGH-SIDECMOSLD MOS (LEVEL SHIFTERS) p+ n+ n+ p-wellpn-pCb-subp+pn+n+n+ p n-C d-su
12、b p+p-COM 4AN-978 RevD 2.1 Input Logic Both channels are controlled by TTL/CMOS compatible inputs. The transition thresholds are different from device to device. Some MGDs, (e.g., IRS211x) have the transition threshold proportional to the logic supply VDD(3 to 20 V) and Schmitt trigger buffers with
13、hysteresis equal to 10% of VDDto accept inputs with long rise time. Other MGDs (e.g., IRS210x, IRS212x, and IRS213x devices) have a fixed transition from logic 0 to logic 1 between 1.5 V to 2 V. Some MGDs can drive only one high-side power device (e.g., IRS2117, IRS2127, and IRS21851). Others can dr
14、ive one high-side and one low-side power device. Others can drive a full three-phase bridge (e.g., the IRS213x and IRS263x families). It goes without saying that any high-side driver can also drive a low-side device. Those MGDs with two gate drive channel can have dual, hence independent, input comm
15、ands or a single input command with complementary drive and predetermined deadtime. Those applications that require a minimum deadtime should use MGDs with integrated deadtime (half-bridge driver) or a high- and low-side driver in combination with passive components to provide the needed deadtime, a
16、s shown in Section 12. Typically, the propagation delay between input command and gate drive output is approximately the same for both channels at turn-on as well as turn-off (with temperature dependence as characterized in the datasheet). For MGDs with a positive high shutdown function (e.g., IRS21
17、10), the outputs are shutdown internally, for the remainder of the cycle, by a logic 1 signal at the shut down input. The first input command after the removal of the shutdown signal clears the latch and activates its channel. This latched shutdown lends itself to a simple implementation of a cycle-
18、by-cycle current control, as exemplified in Section 12. The signals from the input logic are coupled to the individual channels through high noise immunity level translators. This allows the ground reference of the logic supply (VSS) to swing by 5 V with respect to the power ground (COM). This featu
19、re is of great help in coping with the less than ideal ground layout of a typical power conditioning circuit. As a further measure of noise immunity, a pulse-width discriminator screens out pulses that are shorter than 50 ns or so. 2.2 Low-Side Channel The drivers output stage is implemented either
20、with two n-channel MOSFETs in the totem pole configuration (source follower as a current source and common source for current sinking), or with an n-channel and a p-channel CMOS inverter stage. Each MOSFET can sink or source gate currents from 0.12 A to 4 A, depending on the MGD. The source of the l
21、ower driver is independently brought out to the COM pin so that a direct connection can be made to the source of the power device for the return of the gate drive current. The relevance of this will be seen in Section 5. An undervoltage lockout prevents either channel from operating if VCCis below t
22、he specified value (typically 8.6/8.2 V). Any pulse that is present at the input pin for the low-side channel when the UV lockout is released turns on the power transistor from the moment the UV lockout is released. This behavior is different from that of the high-side channel, as we will see in the
23、 next subsection. 2.3 High-Side Channel This channel has been built into an “isolation tub” (Figure 3) capable of floating from 500 V or 1200 V to -5 V with respect to power ground (COM). The tub “floats” at the potential of VS.Typically this pin is connected to the source of the high-side device, a
24、s shown in Figure 2 and swings with it between the two rails. 5AN-978 RevD If an isolated supply is connected between VBand VS, the high-side channel will switch the output (HO) between the positive of this supply and its ground in accordance with the input command. One significant feature of MOS-g
25、ated transistors is their capacitive input characteristic (i.e., the fact that they are turned on by supplying a charge to the gate rather than a continuous current). If the high-side channel is driving one such device, the isolated supply can be replaced by a bootstrap capacitor (CBOOT), as shown i
26、n Figure 2. The gate charge for the high-side MOSFET is provided by the bootstrap capacitor which is charged by the 15 V supply through the bootstrap diode during the time when the device is off (assuming that VSswings to ground during that time, as it does in most applications). Since the capacitor
27、 is charged from a low voltage source the power consumed to drive the gate is small. The input commands for the high-side channel have to be level-shifted from the level of COM to whatever potential the tub is floating at which can be as high as 1200 V. As shown in Figure 2 the on/off commands are t
28、ransmitted in the form of narrow pulses at the rising and falling edges of the input command. They are latched by a set/reset flip-flop referenced to the floating potential. The use of pulses greatly reduces the power dissipation associated with the level translation. The pulse discriminator filters
29、 the set/reset pulses from fast dv/dt transients appearing on the VSnode so that switching rates as high as 50 V/ns in the power devices will not adversely affect the operation of the MGD. This channel has its own undervoltage lockout (on some MGDs) which blocks the gate drive if the voltage between
30、 VBand VS(i.e., the voltage across the upper totem pole) is below its limits. The operation of the UV lockout differs from the one on VCCin one detail: the first pulse after the UV lockout has released the channel changes the state of the output. The high voltage level translator circuit is designed
31、 to function properly even when the VSnode swings below the COM pin by a voltage indicated in the datasheet (typically 5 V). This occurs due to the forward recovery of the lower power diode or to the LdI/dt induced voltage transient. Section 5 gives directions on how to limit this negative voltage t
32、ransient. 2.4 Supply Clamp Many of the MGDs feature integrated supply clamps of 20 V or 25 V to protect against supply transients. Exceeding this clamp voltage for a substantial period of time will cause irreversible damage to the control IC. 3. HOW TO SELECT THE BOOTSTRAP COMPONENTS As shown in Fig
33、ure 2, the bootstrap diode and capacitor are the only external components strictly required for operation in a standard PWM application. Local decoupling capacitors on the VCC(and digital) supply are useful in practice to compensate for the inductance of the supply lines. The voltage seen by the boo
34、tstrap capacitor is the VCCsupply only. Its capacitance is determined by the following constraints: 1. Gate voltage required to enhance MGT 2. IQBS- quiescent current for the high-side driver circuitry 3. Currents within the level shifter of the control IC 4. MGT gate-source forward leakage current
35、5. Bootstrap capacitor leakage current 6AN-978 RevD Factor 5 is only relevant if the bootstrap capacitor is an electrolytic capacitor, and can be ignored if other types of capacitor are used. Therefore it is always better to use a non-electrolytic capacitor if possible. For more detailed informatio
36、n on bootstrap component selection see DT98-2a “Bootstrap Component Selection for Control ICs.” The minimum bootstrap capacitor value can be calculated from the following equation: CQIfQIfVVVgqbslsCbs leakcc f LS+22(max) ( )VMinwhere: Qg = Gate charge of high-side FET f = frequency of operation ICbs
37、 (leak)= bootstrap capacitor leakage current Iqbs (max)= Maximum VBSquiescent current VCC= Logic section voltage source Vf = Forward voltage drop across the bootstrap diode VLS = Voltage drop across the low-side FET or load VMin= Minimum voltage between VBand VS. Qls= level shift charge required per
38、 cycle (typically 5 nC for 500 V/600 V MGDs and 20 nC for 1200 V MGDs) The bootstrap diode must be able to block the full voltage seen in the specific circuit; in the circuits of Figures 25, 28 and 29 this occurs when the top device is on and is about equal to the voltage across the power rail. The
39、current rating of the diode is the product of gate charge times switching frequency. For an IRF450 HEXFET power MOSFET operating at 100 kHz it is approximately 12 mA. The high temperature reverse leakage characteristic of this diode can be an important parameter in those applications where the capac
40、itor has to hold the charge for a prolonged period of time. For the same reason it is important that this diode have an ultra-fast recovery to reduce the amount of charge that is fed back from the bootstrap capacitor into the supply. 4. HOW TO CALCULATE THE POWER DISSIPATION IN AN MGD The total loss
41、es in an MGD result from a number of factors that can be grouped under low voltage (static and dynamic) and high voltage (static and dynamic) conditions. a) Low voltage static losses (PD,q(LV) are due to the quiescent currents from the low voltage supplies (e.g., VDD, VCCand VSS). In a typical 15 V
42、application these losses amount to approximately 3.5 mW at 25 C and increase to approximately 5 mW at TJ= 125 C . b) Low voltage dynamic losses (PD,SW(LV) on the VCCsupply are due to two different components: 1. Whenever a capacitor is charged or discharged through a resistor, half of the energy tha
43、t goes into charging the capacitance is dissipated in the resistor. Thus, the losses in the gate drive resistance (internal and external to the MGD) for one complete cycle is the following: PG= V QG f 7AN-978 RevD For two IRF450 HEXFETs operated at 100 kHz with Vgs= 15 V, we have: PG= 2(15 V)(120 n
44、C)(100 kHz) = 0.36 W The factor 2 in the formula is valid in the assumption that two devices are being driven, one per channel. If VSSis generated with a bootstrap capacitor/diode, this power is supplied from VCC. The use of gate resistors reduces the amount of gate drive power that is dissipated in
45、side the MGD by the ratio of the respective resistances. If the internal resistance is 6 , sourcing or sinking, and if the gate resistor is 10 , only 6/16 of PGis dissipated within the MGD. These losses are not temperature dependent. 2. Dynamic losses associated with the switching of the internal CM
46、OS circuitry can be approximated with the following formula: PCMOS= VCC QCMOS f with QCMOSbetween 5 and 30 nC, depending on MGD. In a typical 100 kHz application these losses would amount to tens of mW, (these losses are largely independent of temperature). c) High voltage static losses (PD,Q(HV) ar
47、e mainly due to the leakage currents in the level shifting stage. They are dependent on the voltage applied to the VSpin and they are proportional to the duty cycle, since they only occur when the high-side power device is on. If VSis kept continuously at 400 V they would typically be 0.06 mW at 25
48、C and increase to approximately 2.25 mW at 125 C. These losses would be virtually zero if VSis grounded, as in a push-pull or similar topology. d) High voltage switching losses (PD,SW(HV) comprise two terms, one due to the level shifting circuit (see Figure 2) and one due to the charging and dischar
49、ging of the capacitance of the high-side p-well (Cb-subin Figure 3). 1. Whenever the high-side flip-flop is reset, a command to turn-off the high-side device (i.e., to set the flip-flop) causes a current to flow through the level-shifting circuit. This charge comes from the high voltage bus through the power device and the bootstrap capacitor. If the high-side flip-flop is set and the low-side power device is on, a command to reset it causes a current to flow from VCC, through the diode.
