1、 AD9361 Initialization and Factory Calibration Guide AD9361 Calibration Guide ADI Confidential Page 2 of 18 TABLE OF CONTENTS Overview 3 Initialization Calibrations 4 BBPLL VCO Calibration . 5 RF Synthesizer Charge Pump Calibration 5 RF Synthesizer VCO calibration. 5 Baseband RX Analog Filter Calibr
2、ation 7 Baseband TX Analog Filter Calibration 8 Baseband TX Secondary Filter . 9 RX TIA Calibration Equations . 10 RX ADC Setup 12 Baseband DC Offset Calibration 13 RF DC Offset Calibration . 14 RX Quadrature Calibration 14 TX Quadrature Calibration 15 Factory Calibrations . 17 Internal DCXO . 17 TX
3、 RSSI (TX Monitor) 17 RX RSSI . 17 RX GM / LNA Gain Step Calibration 18 TX Power Out Vs TX Attenuation and TX Power Out Vs Carrier Frequency 18 REVISION HISTORY 4/2010Rev 0.1 Initial Document 4/2010Rev 0.2 Updated TX Secondary Filter example code 4/2010Rev 0.3 Added max calibration time for BBPLL VC
4、O calibration 4/2010Rev 0.4 Corrections to calibration time equations 10/2010Rev 0.5 Added single shot RX Quadrature Calibration procedure and ADC equations. 3/2011Rev 1.0 Updated FDD register moved to register 0x0130. RF VCO calibration updated. 4/2011Rev 1.1 RF VCO calibration updated to show exam
5、ple calibration times. 6/2011Rev 2.0 General updates 9/2011Rev 2.1 General updates before final review 10/2011Rev 2.2 General formatting updates 2/2012Rev 2.3 Removed TX Monitor DC Offset calibration (unnecessary) and updated TX Quadrature Calibration details ADI Confidential AD9361 Calibration Guid
6、e Page 3 of 18 OVERVIEW The AD9361 powers up into a SLEEP state for minimal power consumption. Before the AD9361 is operational, its clocks must be enabled and initial calibrations completed as shown in the example scripts generated from the AD9361 Evaluation Software. The purpose of this document i
7、s to describe in detail the operation of the different initialization calibrations as well as suggested factory calibrations. Table 1 below lists the initialization calibrations documented in this guide. Table 2 below shows the factory calibrations suggested in this guide. # Calibration Run Frequenc
8、y Calibration Done Bit 1 BBPLL VCO Calibration Once, Any time BBPLL Frequency changes 0x5E7, 1 when locked 2 RF Synthesizer Charge Pump Calibration Once RX: 0x2447, 1 when done TX: 0x2847, 1 when done 3 RF Synthesizer VCO calibration Occurs automatically when integer frequency word written. In TDD,
9、occurs when TXNRX changes logic level. RX: 0x2471, 1 when locked TX: 0x2871, 1 when locked 4 Baseband RX Analog Filter Tune Once, update when BW changes 0x0167, Self clears when done 5 Baseband TX Analog Filter Tune Once, update when BW changes 0x0166, Self clears when done 6 Baseband TX Secondary F
10、ilter T une Once - Manual Equations, update when BW changes 7 RX TIA Calibration Once - Manual Equations, update when BW changes 8 RX ADC Setup Once Manual LUT or equations, update when ADC sampling rate changes 9 Baseband DC Offset Once 0x0160, Self clears when done 10 RF DC Offset Any time LO Freq
11、uency changes more than 100 MHz 0x0161, Self clears when done 11 RX Quadrature Calibration Any time LO Frequency changes more than 100 MHz Tracking runs continuously 12 TX Quadrature Calibration Any time LO Frequency changes more than 100 MHz 0x0164, Self clears when done Table 1: Initialization Cal
12、ibrations Detailed in this Document # Factory Calibration 1 Internal DCXO (AFC tune range) 2 TX RSSI (TX Monitor) 3 RX RSSI (Absolute Power Correlation) 4 RX GM / LNA Gain Step Error 5 TX Power out Vs TX attenuation 6 TX Power out Vs Frequency Table 2: Factory Calibrations Detailed in this Document
13、AD9361 Calibration Guide ADI Confidential Page 4 of 18 INITIALIZATION CALIBRATIONS Initialization calibrations are calibrations that must be run each time the AD9361 device is powered up or hard reset using the RESETB pin. Several of the calibrations only need to run once during initialization. Othe
14、rs are dependent on the carrier frequency, temperature, or other parameters and need to run initially and when certain events occur (such as changing the carrier frequency more than 100 MHz). As long as power is applied to the AD9361 device, the calibration results are stored in the SPI register map
15、, including while in the SLEEP state. Calibrations should be run in the order shown in the example scripts generated from the AD9361 Evaluation Software. Reg Name D7 D6 D5 D4 D3 D2 D1 D0 0x016 Calibration Control RX BB Tuning (self clear) TX BB Tuning (self clear) RX Quad cal (self clear) TX Quad ca
16、l (self clear) RX Gain Step Cal (self clear) TX Monitor DC cal (self clear) RF DC cal (self clear) Baseband DC cal (self clear) 0x017 STATE calibration sequence state3:0 ensm_state3:0 Table 3: AD9361 Registers to Start/Monitor Calibrations The six calibrations in 0x0165:0 are part of a calibration s
17、equence state machine and are enabled by setting the corresponding start bit in register 0x016. After a calibration completes, the corresponding bit in 0x016 will self clear. If more than one calibration is enabled in a single register write, the calibrations will progress in a set order controlled
18、by a state machine in the AD9361. The table below shows the sequence of calibrations. When the calibration sequence state (0x0177:4) holds a value of 0x1, the calibrations are complete. Before a calibration is run, register settings for that calibration should be written as shown in a generated init
19、ialization script from the AD9361 Evaluation Software. Some calibrations depend on the results of previously run calibrations. The RX baseband filter and TX baseband filter calibrations in 0x0167:6 are not part of the calibration sequence state machine, and should run only when all other calibration
20、s are NOT running. Calibration sequence state3:0 Active Calibration 0x0 Calibration W AIT State 0x1 Calibrations Done 0x2 Baseband DC Offset Calibration 0x3 RF RX DC Offset Calibration 0x4 TX1 Quadrature Calibration 0x5 TX2 Quadrature Calibration 0x6 RX1 Quadrature Calibration 0x7 RX2 Quadrature Cal
21、ibration 0x8 TX Monitor Calibration (DC Offset) 0x9 RX GM LNA Gain Step Calibration 0xA 0xF Flush states Table 4: Automatic Calibration Sequence and Calibration Status ADI Confidential AD9361 Calibration Guide Page 5 of 18 BBPLL VCO CALIBRATION The BBPLL VCO calibration must be run during initializa
22、tion of the AD9361 device. The VCO calibration can be disabled by writing register 0x04B=0x40 (clearing 0x04B7). When 0x04B7 is set, a calibration will start when 0x03F2 is set. The calibration start bit in register 0x03F2 does not self clear, and must be manually cleared before another calibration
23、can be started. The maximum BBPLL VCO calibration time is shown below. Register 0x05E7 will equal 1 when the BBPLL is locked. ( ) 128 3 _ _ 1 max + = Counter Scale ing DivideSett IN CLK REF BBPLL VCOcalTimeScale is the value selected in register 0x0451:0. Counter is derived from the value in registe
24、r 0x04B6:5. 0x0451:0 Scale 0x04B6:5 Counter 0x4E4 Divide Setting 00 1 00 128 0 1 01 01 256 1 4 10 10 512 11 2 11 1024 Table 5: BBPLL VCO Cal Time Variables RF SYNTHESIZER CHARGE PUMP CALIBRATION The charge pump calibration must be run once during initialization of the AD9361 device. This calibration
25、 matches the up and down currents for the R F P L Ls charge pump. This calibration must be run the first time the AD9361 device enters the ALERT state. The calibration completes after a maximum of 36864 (REF_CLK_IN * Scale) cycles. The Scale parameter is shown in the table below. 0x2AB0, 0x2AC7 RX R
26、EFCLK Scale 0x2AC3:2 TX REFCLK Scale 00 1 00 1 01 01 10 10 11 2 11 2 Table 6: RX and TX Synth REFCLK Frequency Scale Settings. With a 40MHz REF_CLK_IN, the calibration would complete in less than 921.6us. Please note the sequence of register writes in the script generated by the AD9361 Evaluation So
27、ftware for a detailed order of SPI Writes. In general, follow this typical sequence: 1) Set the device up for FDD to ensure both synthesizers are powered up when in ALERT. a. ENSM FDD bit set in 0x0130. b. Dual Synthesizer bit set in 0x0152. 2) Move the device into the ALERT state. 3) Start the RX C
28、P calibration for the RX synthesizer by setting 0x23D2. 4) Wait until the CP Cal Valid bit goes high in register 0x2447. 5) Clear the RX CP calibration enable bit in register 0x23D2. 6) Start the TX CP calibration for the TX synthesizer by setting 0x27D2. 7) Wait until the CP Cal valid bit goes high
29、 in register 0x2847. 8) Clear the TX CP Calibration enable bit in register 0x27D2. If using TDD, finish the remaining initialization calibrations before setting the ENSM and Dual Synth bit for TDD mode to simplify the calibration process. RF SYNTHESIZER VCO CALIBRATION The AD9361 contains two synthe
30、sizers. When using TDD mode, the RX synthesizer is only enabled in the RX state and when in the ALERT state while TXNRX is low. The TX synthesizer is only enabled in the TX state and when in the ALERT state while TXNRX is high. During initial calibrations, it is recommended to set the AD9361 device
31、into FDD mode to enable both synthesizers while in the ALERT state to simplify calibrations. Before running the RF synthesizer VCO calibrations, set the synthesizer and loop filter registers provided by the AD9361 Evaluation Software. The AD9361 Evaluation Software pulls these setup register values
32、from a LUT based on the VCO frequency. AD9361 Calibration Guide ADI Confidential Page 6 of 18 The VCO calibration starts when the integer frequency word is written for a specific synthesizer (register 0x231 for RX, register 0x271 for TX). First, set up any synthesizer setup registers, then write the
33、 fractional frequency words, followed by the integer frequency word writing 0x231 and 0x271 last. The calibration time can be traded off with calibration accuracy. It is recommended for FDD applications, to use the longest calibration for better accuracy since once in the FDD state, it may be a long
34、 time before a synthesizer VCO calibration occurs again. In TDD, the calibration time will need to be set in order to meet the TDD turnaround time, while achieving the most accurate calibration possible. In TDD, the RX VCO calibration will occur each time the receiver synthesizer is powered up (when
35、 TXRNX switches from high to low logic level). The TX VCO calibration will occur each time the transmitter synthesizer is powered up (when TXNRX switches from low to high logic level). 9 _ _ 6 2 1 max + + + + = ALC table count ALC VCOcalTime wait Scale IN CLK REF N N wait wait RFPLL Where, 1 = 0 024
36、, 0 025, , 2 = 8 _ + 18 ( _ ) , = 1 + 0 249 6: 4, 0 289 6: 4, 40 _ = 6 2 1+ 0 23 7, 0 27 7, , = 2 7+ 0 2493:2, 0 2893:2, 0x23D7 0x2496:4 0x2493:2 REFCLK Scale wait 1 (us) wait 2 (us) wait ALC(us) N ALC N coun t Calibration Time (us) 0 0 3 19.20 1 2 1.354 2.083 12 1024 507.729 0 0 3 30.72 1 2 0.846 1
37、.302 12 1024 318.081 0 0 3 40.00 1 2 0.650 1.000 12 1024 244.750 0 0 3 19.20 2 2 0.885 1.042 12 1024 255.073 0 0 3 30.72 2 2 0.553 0.651 12 1024 160.171 0 0 3 40.00 2 2 0.425 0.500 12 1024 123.475 Table 7: Example Calculated VCO Calibration Times for FDD Default Settings 0x23D7 0x2496:4 0x2493:2 REF
38、CLK Scale wait 1 (us) wait 2 (us) wait ALC(us) N ALC N coun t Calibration Time (us) 0 0 1 19.20 1 2 1.354 2.083 12 128 87.729 0 0 1 30.72 1 2 0.846 1.302 12 128 55.581 0 0 1 40.00 1 2 0.650 1.000 12 128 43.150 0 0 1 19.20 2 2 0.885 1.042 12 128 45.073 0 0 1 30.72 2 2 0.553 0.651 12 256 47.671 0 0 1
39、40.00 2 2 0.425 0.500 12 256 37.075 Table 8: Example Calculated VCO Calibration Times for TDD Defaults The ADI evaluation software default calibration settings are highlighted in blue in the tables above. Please note that the calculated calibration time does not include the synthesizer lock time aft
40、er the calibration is complete. The Synth LUT used determines the VC Os Kv and will dictate the Ncount needed for an accurate RF VCO calibration. The VCO calibrations can be masked (disabled) for certain cases such as the Fast Lock synthesizer mode, or when an HFDD application is desired by setting
41、0x2300 for RX and 0x2700 for TX. Using the FDD Synth LUT could be used to acquire a temperature stable lock for cases where there is not time to run the VCO calibration in TDD. For applications where the RF frequency needs to be corrected in small frequency steps, a RF Frequency correction word can
42、be written in register 0x24E and 0x24F for the RX synthesizer, or 0x28E and 0x23F for the TX synthesizer. Writing the correction word will not start a VCO calibration. ADI Confidential AD9361 Calibration Guide Page 7 of 18 Calibration completion can be detected by reading the RX PLL lock bit in regi
43、ster 0x2471. The TX PLL lock bit is located in 0x2871. The lock bits will read logic 1 when the PLLs are locked. BASEBAND RX ANALOG FILTER CALIBRATION The baseband RX analog filter calibration tunes the cutoff frequency of the 3 rdorder Butterworth RX anti-aliasing filter. The RX filter is located j
44、ust before the ADC in the RX signal path. This calibration is important for RX interferer rejection. The calibration time depends on the RX filter tune clock frequency. The RX filter tune clock frequency is calculated based on the desired baseband bandwidth. NOTE: The BBBW is half the complex bandwi
45、dth and coerced between 28 MHz to 0.20 MHz for the equations used in this filter tuning. ) 2 ln( 2 * * 4 . 1 _ BBBW f Desired RXTuneCLK = To generate this RXTuneCLK, the BBPLL is divided down using a divide by 1 to 511 divider dedicated to the RX tuner block. Before starting the RX baseband filter t
46、une, set this divider value using the following equation. ) _ _ ( , 511 min( 0 : 8 RXTuneCLK f Desired Freq BBPLL ceiling e RXBBFDivid = Typical Sequence: 1) Follow the order of events in the scripts generated by the AD9361 Evaluation Software. 2) AD9361 should be in the ALERT state and previously d
47、iscussed calibrations already run. Verify that no other calibrations are currently running. 3) Set RX baseband filter divide value in register 0x1F87:0 and 0x1F90. Be sure to retain the correct settings in 0x1F97:1. 4) Write the BBBW into registers 0x1FB and 0x1FC. 0x1FB holds the MHz portion, and 0x1FC holds the KHz portion. Register 0x1FB has a step size of 1MHz/LSB, while 0x1FC is written using the following equation : ( ) ) 8125 . 7 1000 * ) ( ( , 127 min( 0 : 6 _ MHz MHz BBBW Floor BBBW Round KHz RXTuneBBB
