1、Introduction To VHDL,outline,0. What is VHDL1. VHDL Description of Combinational Networks2. VHDL Models for a Multiplexer3. Modeling Flip-flops using VHDL Processes4. Compilation and Simulation of VHDL Code5. Modeling a Sequential Machine6. Variables, Signals, and Constants7. Arrays and Records8. VH
2、DL Operators9. VHDL Functions 10. VHDL Procedures 11. Hierarchical design 12. VHDL Mode for a 74163 Counter 13. Addition Topics,2,0.What is VHDL,VHDL Very High Speed Integrated Circuit (VHSIC)Hardware Description Language Hardware description, simulation and synthesis Developed by TI, IBM, Intermetr
3、ics in 1983 IEEE Std 1076-1987 and 1993 VHDL is a Hardware Description Language, not a programming language. Describes hardware at different levels Data flow (logic equation), Behavioral and structural,3,Example,entity and_2 is - The Entity port (a, b: in std_logic; -describes the input/output PinsY
4、 : out std_logic); end and_2;architecture dataflow of and_2 is -The architecture begin -describes the boxY=a and b; - and Gate end dataflow;,4,Pin,Die,1. VHDL Description of Combinational Networks,布林式： E=C+D=AB+D C=AB 與 E=C+D VHDL式： Concurrent statements C = A and B after 5ns; E = C or D after 5ns;
5、If delay is not specified, “delta” delay is assumed C = A and B ; E = C or D; clock This statement executes repeatedly clk = not clk after 10ns; This statement causes a simulation error clk = not clk;,5,Fig1. logic circuit,Entity-Architecture Pairs,ENTITY ENTITY描述以Entity.IS.End表示 ENTITY用來宣告電路的外部包裝 A
6、rchitecture ArchitectureofIS.BeginEnd表示 描述ENTITY所涵蓋電路的行為和動作 依描述風格可分為下列三種型式： 結構性描述(Structure Description) 資料流描述（Dataflow Descriptions） 行為性描述（Behavioral Description）,6,Entity-Architecture Pairs,Interface-signal-declaration list-of-interface-signals : mode type :=initial-value Mode type In：表示該腳位要從外界接收信
7、號 Out：該腳位將傳送信號到外界 Inout：可收送雙向模式的Port信號 Buffer：表示緩衝模式的Port訊號,7,8,Fig2. architecture of entity-architecture pair,資料流描述(Dataflow Descriptions）,利用布林方程式來表現各信號之間的布林代數關係 屬於並行(Current)敘述的方式 直接設定敘述 A=B; -將訊號B傳遞到A Note: = is signal assignment A=B after 10ns ; Example: architecture Dataflow of NAND2 is beginC=
8、A nand B; end Dataflow;,9,資料流描述(Dataflow Descriptions）,條件指定敘述 When else With select elseY = 1 when X=“010“ else1 when X=“110“ else0;,10,行為性描述(Behavioral Description),使用Process敘述的方式來完成（Sequential 執行模式） 屬於高階描述方式(High-level Description),11,architecture behavior of AND2 is beginprocess (A,B) beginif (A=
9、1) and (B=1) then C=0;else C=1;end if ;end process; end behavior;,結構性描述(Structure Description),ARCHITECTURE structure OF NAND2 ISsignal I:BIT;component AND_2 -NAND元件與其腳位宣告port ( I1,I2 : in bit;O1 : out bit );end component;component INVERTER -NOT元件與其腳位宣告port ( I1 : in bit;O1 : out bit );end component
10、; BEGINCell1:AND_2 port map(I1=A, I2=B, O1=I); -NAND腳位連線關係Cell2:INVERTER port map(I1=I, O1=C); -NOT 腳位連線關係 END structure;,12,VHDL Program Structure,13,Fig3. VHDL program structure,Example : Not Gate,library ieee; use ieee.std_logic_1164.all;entity examp1_not isport( a : in std_logic;y : out std_logi
11、c); end examp1_not; architecture a of examp1_not is beginy = not a; end a;,14,架構宣告區,單體宣告區,Use宣告區&標準定義宣告庫,2 VHDL Models for a Multiplexer,組合邏輯電路(Combinational logic circuit) 資料流描述(Dataflow Descriptions） 直接設定敘述 = ： gets the value of 條件指定敘述 When else With select when,15,Example : Full Adder,16,Fig4. VH
12、DL program of Full Adder,Example : 邏輯電路,17,library IEEE; use IEEE.STD_LOGIC_1164.all;entity bol_vhdl is port ( A,B,C: in STD_LOGIC; D : out STD_LOGIC); end bol_vhdl;architecture a of bol_vhdl is beginD = (not A) and B and (not C)or (A and B and (not C); end a;,Tab1. true table of CLC,Example :解碼器(De
13、coder)2*4,18,library IEEE; use IEEE.STD_LOGIC_1164.all;ENTITY decoder2_4 IS PORT (S1,S0 : IN STD_LOGIC;m0,m1,m2,m3 : OUT STD_LOGIC); END decoder2_4;ARCHITECTURE a OF decoder2_4 IS BEGINm0=(not S1)and (not S0); -00m1=(not S1)and S0; -01m2=S1 and (not S0); -10m3=S1 and S0; -11 END a;,Tab2. true table
14、of 2*4 decoder,Example :四對一多工器,19,library IEEE; use IEEE.STD_LOGIC_1164.all;ENTITY MUX2_4 IS PORT (S1,S0,d0,d1,d2,d3 : IN STD_LOGIC;Y : OUT STD_LOGIC ); END MUX2_4;ARCHITECTURE a OF MUX2_4 IS BEGINY = (not S1)and (not S0)and d0)or(not S1)and S0 and d1)or (S1 and (not S0)and d2)or (S1 and S0 and d3);
15、 END a;,條件指定敘述,20,條件式的訊號設定敘述：When-Else訊號Y = 訊號 A When （條件1） Else訊號 B When （條件2） Else訊號 C ；選擇式的訊號設定敘述：With-Select-when With 選擇訊號 X Select訊號Y = 訊號 A When 選擇訊號 X 為m，訊號 B When 選擇訊號 X 為 n，：訊號 Z When Others ；General,Example : When-Else敘述,21,library IEEE; use IEEE.STD_LOGIC_1164.all;entity true_table is po
16、rt (X : IN STD_LOGIC_VECTOR(2 downto 0);Y : OUT STD_LOGIC ); end true_table;architecture a of true_table is beginY = 1 when X=“010“ else1 when X=“110“ else0; end a;,Example : When-Else敘述,22,library IEEE; use IEEE.STD_LOGIC_1164.all;ENTITY decoder2_4w IS PORT ( X : IN STD_LOGIC_VECTOR(1 downto 0);Y0,
17、Y1,Y2,Y3 : OUT STD_LOGIC); END decoder2_4w;ARCHITECTURE a OF decoder2_4w IS BEGINY0 = 1 when X=“00“ else 0; Y1 = 1 when X=“01“ else 0; Y2 = 1 when X=“10“ else 0; Y3 = 1 when X=“11“ else 0; END a;,23,library IEEE; use IEEE.std_logic_1164.all;entity dec24 is port ( X : in std_logic_vector(1 downto 0);
18、en: in std_logic;Y : out std_logic_vector(3 downto 0); end dec24; architecture a of dec24 is beginY =“1000“ when en = 1 and X = “00“ else“0100“ when en = 1 and X = “01“ else“0010“ when en = 1 and X = “10“ else“0001“ when en = 1 and X = “11“ else“0000“; end a;,Example : With-Select-when敘述,24,library
19、IEEE; use IEEE.STD_LOGIC_1164.all;entity true_tablec is port ( X : IN STD_LOGIC_VECTOR(1 downto 0);D : OUT STD_LOGIC ); end true_tablec;architecture a of true_tablec is begin With X SelectD = 0 when “00“,0 when “01“,1 when “10“, 0 when Others; end a;,Example : With-Select-when敘述,25,library IEEE; use
20、 IEEE.STD_LOGIC_1164.all;entity w_s_decoder24 is port( X : IN STD_LOGIC_VECTOR(1 downto 0);Y : OUT STD_LOGIC_VECTOR(3 downto 0); end w_s_decoder24;architecture a of w_s_decoder24 is beginWith X SelectY = “0001” when “00“,“0010” when “01“,“0100” when “10“,“1000” when “11“,“0000” when others ; end a;,
21、Example : With-Select-when敘述,26,library IEEE; use IEEE.STD_LOGIC_1164.all;entity w_s_c42 is port( X : IN STD_LOGIC_VECTOR(3 downto 0);Y : OUT STD_LOGIC_VECTOR(1 downto 0); end w_s_c42;architecture a of w_s_c42 is beginWith X Select Y = “00” when “0001“,“01” when “0010“,“10” when “0100“,“11” when “10
22、00“,“00” when others ; end a;,Example : With-Select-when敘述,27,library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity alu is port ( A, B : in std_logic_vector(7 downto 0); S : in std_logic_vector(2 downto 0); Y : out std_logic_vector(7 downto
23、0); end alu; architecture a of alu is begin with S select Y =(A + B) when “000“,(A - B) when “001“,(A and B) when “010“,(A or B) when “011“,not (A) when “100“,(A xor B) when “101“, A when others; end a;,3. Modeling Flip-flops using VHDL Processes,行為性描述(Behavioral Description) 敘述 並行性敘述 (Current State
24、ments) 順序性敘述 (Sequential Statements),28,29,Sequential Statements,Process 和 If_then_else,Process statement if statementif condition thensequential statementselsif condition then sequential statements else sequential statementsend if;,30,標記名稱:Process （Sensitivity List） begin Process 主體敘述 End Process 標
25、記名稱;,31,Example : 三態緩衝閘,32,library IEEE; use IEEE.std_logic_1164.all;entity tri_gate is port (oe, X : in std_logic;Y : out std_logic); end tri_gate;architecture a of tri_gate is begin process (oe, X)beginif oe = 1 thenY = X;elseY = Z; end if; end process; end a;,Example : AND Gate,33,library IEEE; u
26、se IEEE.std_logic_1164.all;entity AND2_vhdl is port ( A,B : in STD_LOGIC;C : out STD_LOGIC ); end AND2_vhdl;architecture a of AND2_vhdl isbeginprocess (A,B)beginif (A=0) and (B=0) then C=0;elsif (A=0) and (B=1) then C= 0;elsif (A=1) and (B=0) then C= 0; elsif (A=1) and (B=1) then C= 1;end if ;end pr
27、ocess; end a;,- the sensitivity list - define the process section,Example : D型正反器,34,35,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;ENTITY dff_v is PORT( CLK,D : IN STD_LOGIC;Q : OUT STD_LOGIC ); END dff_v;ARCHITECTURE a OF dff_v IS BEGINPROCESS (CLK)BEGIN IF CLKevent AND CLK=1 THEN Q = D;END IF;END P
28、ROCESS; END a;,Example : JK型正反器,36,順序性條件指定敘述,條件式的訊號設定敘述： Case-when Case-when指令本身是敘述組合邏輯的，但它卻必須在Process指令中執行，因此它是序向邏輯指令之一 ,其語法如下:Case 選擇訊號 ISWhen 選擇訊號1 =敘述命令1; When 選擇訊號2 =敘述命令2;:When Others =敘述命令N; End Case;,37,Example : Multiplexer,38,when Sel selectF = I0 when 0,I1 when 1,I2 when 2,I3 when others;
29、,Example : 四對一的多工器設計,39,library IEEE; use IEEE.STD_LOGIC_1164.all;ENTITY mux4to1_case ISPORT ( S : IN STD_LOGIC_VECTOR(1 downto 0);D0,D1,D2,D3 : IN STD_LOGIC; Y :OUT STD_LOGIC ); END mux4to1_case; ARCHITECTURE a OF mux4to1_case IS BEGINprocess(S,D0,D1,D2,D3)BeginCase S ISWhen “00“= Y Y Y Y=D3;End Ca
30、se;End Process; END a;,Example : ALU設計,40,library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_unsigned.all;ENTITY alu IS PORT ( C : in std_logic; S : IN STD_LOGIC_VECTOR(1 downto 0);A,B : IN STD_LOGIC_VECTOR(7 downto 0);F : OUT STD_LOGIC_VECTOR(7 downto 0) ); END alu;,Example : ALU設計,41,AR
31、CHITECTURE a OF alu IS BEGINProcess (s,A,B)BeginIF C=0 then -當C=0時執行邏輯運算Case s ISWhen “00“= F F F F F F F F=A-1; -遞減1End case;END IF;End Process; END a;,Wait 敘述,Wait Until 條件式 Ex：Wait Until CLKevent and CLK=1； Wait On 訊號 Ex： Wait On a,b Wait For 時間表示式 Ex： Wait For 20ns； Ex： Wait For (a*(b+c);,42,Exa
32、mple : D型正反器,43,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;ENTITY dff_v_wait IS PORT( CLK,D : IN STD_LOGIC;Q : OUT STD_LOGIC ); END dff_v_wait;ARCHITECTURE a OF dff_v_wait IS BEGINPROCESS (CLK)BEGINWait Until (CLKevent AND CLK=1);Q = D; END PROCESS; END a;,4 Compilation and Simulation of VHDL Code,44
33、,45,46,5. Modeling a Sequential Machine,47,48,49,50,6 Variables, Signals, and Constants,signal statementsignal list_of_signal_names : type_name := initnal_value ; variable statementvariable list_of_signal_names : type_name := initnal_value ; constant statementconstant list_of_signal_names : type_nam
34、e := initnal_value ;,51,Signals 訊號可以用來宣告所有元件內部的信號線或內接腳位 。 Signal A：Std_Logic_vector(4 downto 0); Variables An Object Whose Value May be Changed After Creation. Variable temp: Std_logic:= 0; Constants 在VHDL語言中，我們將固定值宣告成常數。 類以C語言中以#define來設定常數值的作法。 Constant A: Std_logic_vector(3 downto 0):=“0011”;,52,
35、Aliases 若有一條匯流排需要區分成數束不同的子線連接到各個地方去時，我們就可以將原來的母線分開來各自命名，宣告每一束子線並各給其一個別名(Aliases)。 Signal A_Bus: Std_Logic_Vector(31 downto 0); Alias Bank1 : Std_Logic_Vector(7 downto 0) IS A_Bus (31 downto 24); Alias Cal_D : Std_Logic_Vector(15 downto 0) IS A_Bus (23 downto 8); Alias Rank : Std_Logic_Vector(7 downt
36、o 0) IS A_Bus (7 downto 0);,53,54,Enumerated Data Type 列舉式資料型別（Enumeration type）是一種集合種類的宣告。 Type std_ulogic IS (U, X ,0, 1, Z, W, L ,H, -); Type week IS (Mon, Tue, Wed, Thu, Fri, Sat, Sun);,55,7 Arrays and Records,56,57,58,Record Data Type 記錄資料型別（Record types）是由兩種或兩種以上資料型別所構成。Type MU2 IS RecordDin,D
37、out: bit_vector(7 downto 0);S:bit;End Record;,59,8 VHDL Operators,60,邏輯運算子,not and or xor nand xnor,61,library ieee; use ieee.std_logic_1164.all;ENTITY log_ex ISPORT( A,B :in std_logic_vector(0 to 3);Y :out std_logic_vector(0 to 3);Z :out std_logic); end log_ex; architecture a of log_ex isbegin Y(0)
38、 = A(0) AND B(0) ;Y(1) = A(1) OR B(1) ;Y(2) = A(2) NOR B(2) ;Y(3) = A(3) XOR B(3) ;Z = (not A(0) nand B(0); end A;,關係運算子,= , /= , , =,62,library ieee; use ieee.std_logic_1164.all;ENTITY rel_ex ISPORT( A,B,C,D,E,F:in std_logic_vector(2 downto 0);Y: out std_logic); end rel_ex; architecture behavior of
39、 rel_ex is begin process (A,B,C,D,E,F)beginif (A=B) or (CD) and not(E=F) theny=1;elsey=0;end if;end process; end behavior;,算術運算子,+ (加) - (減) * (乘) / (除) *(次方),63,library IEEE; use IEEE.Std_logic_1164.all; use IEEE.Std_logic_unsigned.all;entity arith_ex is port (A,B : in integer range 7 downto 0;C,D
40、: out integer range 64 downto 0;E,F,G : out integer range 7 downto 0 ); end arith_ex; architecture a of arith_ex is beginC = A * B; D = 4*2; E = 4 mod 2; F = 6/2; G = 11 REM 3; end a;,數值運算子,64,SLA,SRA,SLL,SRL,ROL,ROR,A sll 2 為 “01010100” A srl 3 為 “00010010” A sla 3 為 “10101111” A sra 2 為 “11100101”
41、 A rol 3 為 “10101100” A ror 5 為 “10101100”,9 VHDL Functions,65,LOOP敘述,FOR-LOOP,66,LOOP敘述,67,While-Loop,LOOP 敘述,Loop,68,NEXT敘述,NEXT敘述的目的是用來中斷某次迭代的迴圈運算，而直接跳到下一次迴圈的開頭重新執行迴圈的運算；在某些時候若我們需要直接跳出迴圈時，就可以使用EXIT敘述來完成。 例如： LOOP_A:FOR I IN (1 TO 10) LOOP命令敍述 LOOP_B:FOR J IN (1 TO 10) LOOP命令敘述NEXT LOOP_A WHEN (J=
42、I);END LOOP LOOP_B; END LOOP LOOP_A;,69,EXIT 敘述,當程式執行發生重大錯誤或是所有程序早已執行完畢時，使用EXIT敘述可以用來中斷整個迴圈敘述。 例如： For I IN 0 TO N LOOPIF (a=0) then - a 必須維持大於0，否則跳離迴圈EXIT;Elsea:=a-1;Q(i)=3.14/Real(a*I);End if; End LOOP;,70,NULL 敘述,NULL敘述就是空敘述，維持電路原來的運作狀況。 例如：Case S ISWHEN “00”=YYNULL;END CASE;,71,72,10 VHDL Proced
43、ures,procedure statementprocedure procedure_name (formal-parameter-list) isdeclarationsbeginsequential statementsend procedure_name,73,11 Hierarchical design,結構性描述(Structure Description) Components Packages,74,Component 與Port Map,Component的功能能夠協助我們作元件資料庫的設計，它與Port Map結合可以讓我們利用現有的component像堆積木一般累積出複雜
44、的電路。 Port Map腳位設定的方式如下: 位置對應表示式 (must match the port order) 對應:一個蘿蔔一個坑 名稱對應表示式: 對應:signal = port_name FA1: full_adder PORT MAP (Cin=x, a0=y, b0=z, S0=Sum, t1=Carry);,75,Component 與Port Map,signal X1, X2, X3, X4 : std_logic; Begin U1: NAND3_OP port map (A, B, C, X1); U2: NAND3_OP port map (A, B, D, X
45、2); U3: NAND3_OP port map (A, C, D, X3); U4: NAND3_OP port map (B, C, D, X4); U5: NAND4_OP port map (X1, X2, X3, X4, F);,76,Example :四對一多工器描述(component),77,library IEEE; use IEEE.STD_LOGIC_1164.all;ENTITY mux4_1 IS PORT ( D0,D1,D2,D3 ,S1,S0 : IN STD_LOGIC; Y : OUT STD_LOGIC); END mux4_1 ;ARCHITECTUR
46、E a OF mux4_1 IS BEGINY=(D0 and (not S1)and (not S0)or (D1 and (not S1)and S0) or (D2 and S1 and (not S0) or (D3 and S1 and S0) ; END a;,Example :利用四對一多工器的component 建立十六對一多工器,78,ARCHITECTURE a OF mux16to1c IS component mux4_1port ( d0,d1,d2,d3, S1,S0 :in std_logic; Y:out std_logic );end component;si
47、gnal m :std_logic_vector(0 to 3);BEGINmux1:mux4_1 port map(d(0),d(1),d(2),d(3),S(1),S(0),m(0);mux2:mux4_1 port map(d(4),d(5),d(6),d(7),S(1),S(0),m(1);mux3:mux4_1 port map(d(8),d(9),d(10),d(11),S(1),S(0),m(2);mux4:mux4_1 port map(d(12),d(13),d(14),d(15),S(1),S(0),m(3);mux5:mux4_1 port map(m(0),m(1),m
48、(2),m(3),S(3),S(2),Y);END a;,Example :全加器電路設計,79,ARCHITECTURE a OF fulladder IScomponent halfadderport ( a,b :in std_logic;s,c : out std_logic );end component;component or_2port ( a,b :in std_logic;c :out std_logic );end component;signal s1,s2,s3 :std_logic; BEGINU1:halfadder port map(x,y,s1,s3);U2:
49、halfadder port map(s1,z,sum,s2);U3:or_2 port map(s2,s3,carry); END a;,80,Example :暫存器,81,Architecture a of REGH_4 iscomponent AND_2PORT( A,B:in std_logic;Z :out std_logic);end component;component DFF_VPORT( D,CLK : IN std_logic;Q : OUT std_logic );end component;signal int_clk : std_logic; beginIC0 : dff_v port map ( d0, int_clk, q0 );IC1 : dff_v port map ( d1, int_clk, q1 );IC2 : dff_v port map ( d2, int_clk, q2 );IC3 : dff_v port map ( d3, int_clk, q3 );IC4 : and_2 port map ( en, clk, int_clk ); end a;,
