1、 1 三态门 library ieee; use ieee.std_logic_1164.all; entity three is port( a,en:in std_logic; y:out std_logic); end three; architecture bhv of three is begin process(a,en) begin if en=1 then yb else “010“ when a=b else “001“ when aledledledledledledledledledled2) port map(d(0 to 1),y1); u2:andn generic
2、 map(n=3) port map(d(2 to 4),y2); end hbv; 6. 七人表决器library ieee;use ieee.std_logic_1164.all;entity vote7 isport(a:in std_logic_vector( 0 to 6);lg,lr:out std_logic);end;architecture bhv of vote7 issignal pass:integer;beginprocess(a)variable tmp1:integer;begintmp1:=0;for i in 0 to 6 loopif a(i)=1 then
3、 tmp1:=tmp1+1; else tmp1:=tmp1+0;end if;end loop;pass=4 else 0;lrif din=d(7)then sif din=d(6)then sif din=d(5)then sif din=d(4)then sif din=d(3)then sif din=d(2)then sif din=d(1)then sif din=d(0)then ss=0;end case; end if;end process;p2:process(s)begin if s=8 then y=1;else y=0;end if;end process;end
4、 b;8. 4 选 1 数据选择器的设计（设计方法不唯一）library ieee;use ieee.std_logic_1164.all;entity mux41 isport(a,b,en:in std_logic;d:in std_logic_vector(0 to 3);y:out std_logic);End mux41;architecture bhv of mux41 issignal sel:std_logic_vector(0 to 1);beginsel=awith sel selecty=d(0) when “00“,d(1) when “01“,d(2) when “10“,d(3) when “11“,Z when others;end bhv;
