1、Version 1.0 Page 1 of 17 Q408Implementation and Timing of Reset Circuits in Altera FPGAsABSTRACTMost circuit designs employing FPGAs and ASICs are synchronous systems using a large number of flip-flops or registers. It is usually important that these synchronous elements are capable of starting or b
2、eing returned to a known state (logic 1 or 0). This function is normally handled by a reset. There are usually one or more reset signals that are brought into the device and used, alone or in conjunction with additional circuitry to perform this function. This Tech Note examines the various types of
3、 resets; synchronous, asynchronous, and synchronized asynchronous with respect to their advantages and disadvantages, various techniques of implementation in FPGAs, and their proper timing analysis in Alteras TimeQuest timing analysis engine.Synchronous circuits are typically reset with one of two t
4、ypes of resets; synchronous or asynchronous resets. Synchronous resets are frequency synchronous with the clock domain of the registers they reset. Asynchronous resets by nature will arrive at the registers they are affecting with a non-deterministic timing relationship to the clock domain of the re
5、gisters. Because of this, it is difficult to time these types of resets. A third category or resets is discussed here which, for the lack of a better name, will be referred to as synchronized asynchronous resets. These resets have some of the benefits of synchronous resets without some of their disa
6、dvantages, and they also avoid some of the pitfalls that can be associated with purely asynchronous resets. As shall be shown, for most situations, synchronized asynchronous resets are the preferred method when designing FPGA circuits.Synchronous ResetsSynchronous resets are based on the premise tha
7、t the reset signal will only affect the state of a register on the active edge of the clock signal to that register. Synchronous resets have the advantage that they generally insure that the circuit is 100% synchronous. They also have the advantage that they can be easily timed with static timing an
8、alysis tools such as the Altera Quartus II TimeQuest timing engine. Since the reset signal is launched and latched by clocks that are synchronous to each other, the Data Arrival and Data Required times can be easily determined for proper slack analysis. Another advantage of synchronous resets is tha
9、t they can be much easier to work with when using cycle-based simulators.These resets do have their disadvantages however. For example, they may require pulse stretchers to guarantee a reset pulse width wide enough to ensure reset is present during an active edge of the clock. Perhaps even more impo
10、rtantly, these resets require a clock in order to reset a circuit. If something is causing the launch clock to fail, the resulting circuit will not get the reset.In Altera FPGAs, there are two methods by which a reset can reach a register; either by being gated in with the data input (see Figure 1),
11、 or by using a LAB-wide control signal, synclr (see Figure 2). The first method has the potential disadvantage that an additional gate delay may have to be added to the circuit to accommodate the reset signal causing increased Data Arrival times. In that event, it would have a negative impact on set
12、up slack. The second method relies on dedicated routing in the Logic Array Block (LAB) to each register, but is also slower than an asynchronous reset would be to the same register. Figure 3 shows that the path for synchronous clear traverses an AND gate, whereas the asynchronous clear path goes dir
13、ectly to the register.1 In addition, there is only one synchronous synclr control signal per LAB, but there 1 In fact, this path is slightly slower than the path through the LC. The potential advantage of the LAB-wide synclr is to save on LCs.Version 1.0 Page 2 of 17 Q408are two asynchronous labclr
14、control signals per LAB. Using a large number of synchronous resets in a design can cause the fitter to run out of LABs due to this. However, without the use of these LAB-wide synchronous clear signals, the logic cell (LC) utilization could increase. These are the tradeoffs that must be made when us
15、ing synchronous resets in FPGAs. Fortunately, Quartus II does offer some control over which of these two methods will be used. This can be controlled on a global level, or on a module (entity) level, but not on an individual register level.2 There are two settings that can be assigned in the Assignm
16、ent Editor: ALLOW_SYNCH_CLEAR_USAGE and FORCE_SYNCH_CLEAR. The first setting will allow the synthesis engine to use the LAB-wide synchronous clear signal when needed, and the second one forces the tool to always use it. Either way, synchronous resets will be slower than asynchronous resets and are n
17、ot the preferred method in FPGAs.Figure 1: Synchronous Reset Using Logic CellFigure 2: LAB-Wide Control Signals Stratix III FPGAs2 One could control this on an individual register basis by controlling the source code and by using a synthesis directive to force the tool not to optimize out the gate i
18、n front of the register.Version 1.0 Page 3 of 17 Q408Figure 3: Adaptive Logic Module (ALM) Details Stratix III FPGAsWhen examining the timing analysis of synchronous resets, there are two types that need to be addressed; externally synchronized and internally synchronized. Externally synchronized re
19、sets are synchronized to the clock domain outside the FPGA. These are not very common. Figure 4: Schematic for Externally Synchronized ResetVersion 1.0 Page 4 of 17 Q408An example of an externally synchronized reset is shown in Figure 4. A power-on asynchronous reset por_n is dual-rank synchronized
20、externally to the system clock and then brought into the FPGA. Inside the FPGA, this reset is gated with the data input to the registers to implement a synchronous reset. Figure 5 shows the Verilog equivalent of the schematic. The important thing to note here is that when using synchronous resets, t
21、he reset signal is not put in the sensitivity list as it would be for an asynchronous reset.Figure 5: Verilog Code for Externally Synchronized ResetThe constraints for this design are shown in Figure 6. Since the external reset is synchronous, one only needs to constrain the reset_n signal as a norm
22、al input signal with a set_input_delay statement.Figure 6: SDC Constraints for Externally Synchronized ResetVersion 1.0 Page 5 of 17 Q408More often, resets coming into the device are asynchronous. In this case, the resets must be synchronized internally before being sent to the registers. As shown i
23、n Figure 7, the synchronization registers are now inside the FPGA. Figure 7: Schematic for Internally Synchronized ResetThe equivalent Verilog code is shown in Figure 8. Again, note that only the clock edge is in the sensitivity list for a synchronous reset.Figure 8: Verilog Code for Internally Gene
24、rated ResetVersion 1.0 Page 6 of 17 Q408The SDC constraints are similar to the external case except that now the input reset cannot be constrained since it is asynchronous, and should be cut with a set_false_path statement as shown in Figure 9 to avoid these being considered unconstrained paths.Figu
25、re 9: SDC Constraints for Internally Synchronized ResetAnother issue with synchronous resets is their behavior with respect to short pulses (less than a period) on the asynchronous input to the synchronizer flip-flops. On the one hand, this could be viewed as a disadvantage in that there is a requir
26、ement on the asynchronous reset that it be at least one period wide in order to guarantee that it will be captured by the first flip-flop. On the other hand, this could be viewed as an advantage in that this circuit increases noise immunity. Spurious pulses on the asynchronous input would have a low
27、er chance of being captured by the first flip-flop, so they would not trigger a synchronous reset. In some cases, one might want to increase noise immunity further and reject any asynchronous input reset that is less than n periods wide. This would also be useful for debouncing an asynchronous input
28、 reset. In order to do this, the following modification (Figure 10) should be made to the internally synchronized reset:Figure 10: Schematic for Internally Synchronized Reset with Pulse ExtenderMany designs have more than one clock signal. In these cases, a separate reset synchronization circuit sho
29、uld be used for each clock domain in the design. When PLLs are involved, extra caution should be used. When creating synchronizers for the PLL output clocks, these clock domains will not be reset until the PLL has locked and the PLL output clocks are stable. Also worth noting, if the reset to the PL
30、L is used, this reset does not have to be synchronous to the input clock to the PLL. An asynchronous reset can be used for this. Again, using a reset to the PLL will further delay the assertion of a synchronous reset to the PLL Version 1.0 Page 7 of 17 Q408output clock domains when using internally
31、synchronized resets. As will be demonstrated in a later section of this document, synchronized asynchronous resets solve this problem rather nicely.Asynchronous ResetsAsynchronous resets have been the most common form of resets used in circuit design for a very long time. It has been very popular to
32、 have one asynchronous reset come into the device and then put on a global buffer and connect to the asynchronous reset pin of every (or almost every) register in the device. This approach has its advantages under certain circumstances, but it is not without pitfalls. It is not always the case that
33、every register in a design requires a reset. This approach is not without its costs in terms of routing resources and use of LAB-wide control signals. It is good practice to only reset those registers that require it.One of the biggest advantages of asynchronous resets is that they are not inserted
34、in the data path as synchronous resets are. Hence, they do not negatively impact the data arrival times between registers. Another advantage is that they take effect essentially immediately. As soon as the registers get the reset pulse, regardless of the timing relationship relative to the clock, th
35、e registers are reset. It is not dependent on a clock as synchronous resets are.There isnt any problem with going into reset asynchronously. Problems can arise however when the reset is released, also referred to as “reset removal”. When reset is removed, it must meet the asynchronous tSU time. This
36、 is checked in TimeQuest with a Recovery time check. Also, when reset is removed, it must meet the asynchronous tH time. This is checked in TimeQuest with a Removal time check. Together, these checks are referred to as Recovery/Removal Analysis.3c l o c k0 tS U tHR e c o v e r y T i m e C h e c kR e
37、 l a t i v e D i s t a n c e o f R e s e t D e a s s e r t i o n f r o m C l o c k E d g e tC Or e s e t _ nI n c r e a s e d S e t t l i n g T i m eA d d i t i o n a l D e l a yR e m o v a l T i m e C h e c kM e t a s t a b i l i t y Z o n eFigure 11: Metastability CurveWhen the reset signal is dea
38、sserted and does not pass the recovery or removal time check, the edge is said to have fallen in the metastability zone as shown in Figure 11 above. The consequence of this is that the time it takes for the output of the register to settle to the correct state (based on the data input to the 3 For f
39、urther information on this topic, refer to Tech Note: Understanding Recovery/Removal Analysis in TimeQuest.Version 1.0 Page 8 of 17 Q408register) is increased. This additional delay can lead to setup time failures to registers downstream, leading to system failure. Obviously, this situation should b
40、e avoided at all costs.One method of avoiding this is to add a couple of follower registers after the register with the asynchronous reset and use the output of these registers in the design. The follower registers act to synchronize the data to the clock in a manner to remove the metastability issu
41、es. The closer these registers can be placed to each other in the device, the better to keep the routing delays to a minimum, which decreases data arrival times and increases MTBF. Note that it is important that these follower registers themselves are not reset, but rather will be initialized over a
42、 period of several clock cycles by “flushing out” their current or initial state. Figure 12 below shows a schematic example of this circuit.Figure 12: Schematic of Asynchronous Reset with Follower RegistersIn general, for pipelined designs like this without feedback circuits where there is no sequen
43、ce dependence on initialization, and when the design can wait several cycles after coming out of reset before beginning operation, this type of reset is acceptable.The equivalent Verilog code is shown in Figure 13 below. Note how this differs from the synchronous reset code. The active edge of the r
44、eset is now in the sensitivity list for the procedural block. It is also important that the follower registers are not in the “else” part of the first procedural block as this would infer a clock enable on the follower registers with the inverse of the reset signal tied to the clock enable. The foll
45、ower registers should be in a separate procedural block as shown using non-blocking assignments.Version 1.0 Page 9 of 17 Q408Figure 13: Verilog Code of Asynchronous Reset with Follower RegistersConstraining an asynchronous reset is simple. By definition, asynchronous resets have a non-deterministic
46、relationship to the clock domains of the registers they are resetting. Therefore, static timing analysis of these resets is not possible; they are usually cut with a set_false_path statement (as shown at the bottom of Figure 14). Because the relationship of the reset to the clock at the register is
47、not known, recovery and removal analysis cannot be run in TimeQuest for this path. Attempting to do so will yield no paths reported. Even without the false path statement cutting this path, no paths would be reported for recovery and removal.Figure 14: SDC Constraints for Asynchronous ResetBesides t
48、he potential metastability issues with asynchronous resets, another issue is their susceptibility to noise. A noisy asynchronous reset could cause a spurious reset. For this reason, it is important that the asynchronous reset is debounced and filtered. As mentioned previously, synchronous resets are
49、 less susceptible to this problem (although not immune) because they are registered by the clock. In the next section on Synchronized Asynchronous Resets, methods are discussed for avoiding this problem altogether.Perhaps the biggest problem with asynchronous resets is again related to reset removal. Besides the potential for metastability issues, there is no guarantee that every register connected to the reset will have the same timing relationship to the clock due to register placement and routing within the device. The effect of this is that within a given clock
