1、 2009 Altera Corporation1QuartusII Software Design Series: Timing Analysis 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation2Objectivessquare6 Build SDC files for constraining PLD designssquare6 Verify timing on si
2、mple defaults to target name if not specifiedsquare6 waveform: Indicates clock offset or non-50% duty cycle clocks 50% duty cycle is assumed unless otherwise indicatedsquare6 -add: Adds clock to node with existing clock Without add, warning given and subsequent clock constraints ignoredsquare6 : Tar
3、get ports or pins for clock setting Virtual clock created if no target specified 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation22create_clockExamplescreate_clock period 20.0 name clk_50 get_ports clk_in0 10 20 3
4、0create_clock period 10.0 waveform 2.0 8.0 get_ports sysclk0 2 8 10 12 18 20sysclk (sysclk) -clk_in (clk_50) - 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation23Create Clock using GUIName Finder (next slide)Edit a
5、ny field(change values; use wildcards in targets or command)TimeQuestmain: Constraints Create ClockSDC Editor: Edit Insert Constraint Create Clock 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation24Name Finder Clic
6、king on Browse button opens Name Finder allowing you to search netlistfor node names (similar to QuartusII Node Finder)Select collection to searchEdit command here or final command to use wildcardsOptions available depend on selected collection 2009 Altera CorporationAltera, Stratix, Arria, Cyclone,
7、 MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation26Creating a Generated Clocksquare6 Command: create_generated_clocksquare6 Options -name -source -master_clock -divide_by -multiply_by -duty_cycle -invert-phase -edges -edge_shift -add 2009 Altera CorporationAltera, Stra
8、tix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation27create_generated_clockNotessquare6 source: Species the node in design from which generated clock is derived Ex. Placing source before vs. after an inverter would yield different resultssquare6 maste
9、r_clock: Used if multiple clocks exist at source due to -add optionsquare6 edges: Relates rising/falling edges of generated clock to rising/falling edges of source based on numbered edgessquare6 -edge_shift: Relates edges based on amount of time shifted (requires -edges) 2009 Altera CorporationAlter
10、a, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation28Create Generated Clock using GUI 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation29Generated Clock Examp
11、le 1create_clock period 10 get_ports clk_increate_generated_clock name clk_div source get_pins inst|clk -divide_by 2 get_pins inst|regoutSource pinTarget pin 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation30Gener
12、ated Clock Example 2clk_in1 2 3 4 5 6 7 8pulse_clk_outmaster edgescreate_clock period 10 get_ports clk_increate_generated_clock name pulse_clk_out -source clk_in edges 1 4 5get_pins pulse_logic|out# Master edges are numbered 1. In the edge list, the first# number corresponds to the first rising edge
13、 of the generated# clock. The second number is the first falling edge. The third# number is the second rising edge. Thus, a clock is created that# is half the period of the source with a 75% duty cycle. 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCor
14、e are trademarks of Altera Corporation31Generated Clock Example 3clk_in1 2 3 4 5 6 7 8pulse_clk_outmaster edgescreate_clock period 10 get_ports clk_increate_generated_clock name pulse_clk_out -source clk_in edges 1 4 5 -edge_shift 2.5 2.5 0get_pins pulse_logic|out# Same as example 2 except -edge_shi
15、ft shifts each edge indicated# amount of time 2009 Altera CorporationAltera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation32PLL Clocks (Altera SDC Extension)square6 Command: derive_pll_clocks -use_tan_name: names clock after design net name from Classic timing analyzer settings instead of the default PLL output SDC pin name -create_base_clocks: generates create_clock constraint(s) for PLL input clocks square6 Create generated clocks on all PLL outputs Based on input clock must be entered in SDC manually
