4 线-2 线优先编码器设计、仿真与实现1.真值表：输入 输出I0 I1 I2 I3 Y1 Y01 0 0 0 0 0X 1 0 0 0 1X X 1 0 1 0X X X 1 1 12.逻辑关系Y1 = X0 + X1Y2 = X0 + X1X23.Verolig 代码实现/A 4-2 decordermodule DECODER_4_2(X, Y0, Y1);input 3:0X;output Y0,Y1; wire n0,n1,n2; not (n0,X1);and (n1,n0,X2);assign Y0=(X0|n1); assign Y1=(X0|X1); endmodule4.Quartus II 仿真结果时钟设置：X0 = 10ns x1 = 20ns x2 = 40ns x3 = 80ns输入输出状态表：X0 X1 X2 X3 Y0 Y10 0 0 0 0 01 0 0 0 1 10 1 0 0 0 11 1 0 0 1 10 0 1 0 1 01 0 1 0 1 10 1 1 0 0 11 1 1 0 1 10 0 0 1 0 01 0 0 1 1 10 1 0 1 0 11 1 0 1 1 10 0 1 1 1 01 0 1 1 1 10 1 1 1 0 11 1 1 1 1 15.FPGA 引脚设置
