1、 EMPro2013 & EMI/EMC Design Methodology using Simulations and Measurements Page 1 Avoid EMI Nightmares Agilent EEsof EDA 谢成诚 cheng-cheng_ Agenda EMIC Overview IC, PKG and BRD EMIC Example-1: IC What impacts the harmonics Example-2: BRD Impact of gnd stitching Example-3: BRD Impact of Common-mode Noi
2、se System EMIC Example-4: DDR2 Digital Noise on RF Receiver sensitivity Example-5: BRD Impact of Shielding Example-6: Connector Impact of 3D discontinuities Example-7: Impact of IC Noise on PCB EMI Analysis Features in EMPro 2013 Page 2 What is EMIC? Graphic Source: http:/ Source (Culprit, emitter)
3、Receptor (Victim, Receiver) Transfer (Coupling Path) Conducted Radiated Power Lines Signal Lines Magnetic Electric Planewave Page 3 Improving CHIP EMIC performance Need to model non-ideal IC behavior and understand its impact on EMIC. - Rise/Fall time mismatch - Intra-pair delay - Jitter (RJ, PJ, DC
4、D, ISI) Page 4 Example-1: Simple CKT simulation into test load Page 5 Study Impact of Driver -Rise/Fall time mismatch -Intra-pair Delay -Presence of Random Jitter Matched/Unmatched Clock/Data Pairs PSD Page 6 Matched CLK Pair Un-Matched Data Pair Matched Un-Matched Un-Matched cases show strong prese
5、nce of even harmonics How to address IC & PKG EMI/EMC Page 7 IC PKG CLK/ADDR HIGH-SPEED DATA Step1: Isolate CLK Trace routing close to slots - harsh radiation Size of Reference Plane - patch antenna radiation Lack of GND-Stitching - hot-spots that become radiators Step2: Model High-Speed Data Signal
6、s All of the above Proper referencing Coupling between Data and CLK HIGH-SPEED DATA Why do we need Full-EM accuracy? - Non-Ideal Return Path Slots in reference planes Finite-plane edge effects Number of GND Stitching Vias - Vias Via-to-Via Coupling Via Stubs Antipad effect - Noise Coupling from Refe
7、rence plane to Signal Page 8 Typical EMIC tools make lot of assumptions NOT model real-world effects Board Design for optimum EMIC Same flow as PKG minimize “hot-spots” BRD EMIC performance is highly dependent on layout Bad layout habits Signals passing by or over Slots Signals changing layers witho
8、ut proper GND referencing Signals changing referencing with bad decaps SSO Noise propagation on planes due to lack of proper decaps & perimeter stitching vias on the PCB Page 9 Need to help customers isolate root-cause of EMIC problems Example #2: High-Speed Board Page 10 Isolating the problem Page
9、11 Inspection of layout shows lack of GND stitching Vias Taking Corrective Action Page 12 - Add more GND stitching Vias - Change DP routing to Top layer and avoid Via-to-Via coupling Improved EMIC results Page 13 Much Smaller Radiation Emission Antenna Gain is -41dB Surface Current “hot-spots” are g
10、one with the addition of sufficient GND stitching Vias and Improved layer routing Example #3: Does Common-mode impact EMIC? Page 14 Common-mode current injection to connector Page 15 Example-4: DDR2 Digital Noise on RF Receiver Sensitivity Page 16 Clock Frequency : 266MHz Data Rate : 533Mbps Clock s
11、ignal contains high frequency components around 2.45GHz, which acts as the source of noise Clock Signal Spectrum f p t v Conceptual Approach High frequency component of DDR clock noise may interfere with W-LAN, Bluetooth, and Antenna S-parameter analysis technique will provide insight on the boards
12、frequency selectivity to DDR noise Clock Signal (Broadband Input) f p f p Board s Frequency Selectivity Response PCB Structure (Network) Page 17 Complete Board Simulation in EMPro Very complex multi-layer board Thousands of vias Dozens of ICs Hundreds of passive components Page 18 Test Scenarios 3 d
13、ifferent test scenarios with broadband, 2.45GHz, time-domain clock sources W-LAN Out Ant Bluetooth 2.45G S-parameter Field data Time-Domain PCB CPU Page 19 S-Parameter Analysis: DDR to RF S-parameter analysis technique will provide insight on the boards frequency selectivity to DDR noise Page 20 The
14、 frequency response of DDR2 to W-LAN proves the clock noise couples more than others Networks (PCB Board) Frequency Selectivity W-LAN BT Ant 10+ dB Page 21 Field Data With 2.45GHz Input Field data may provide some insight to the potential coupling paths E-field plots on different layers at 2.45GHz N
15、oise coupled to W-LAN Page 22 Time-Domain Simulation with Differential Clock Signals Directly excited with differential clock signal, Vpp = 1V CPU Page 23 Time Domain Simulation Result Noise voltages are time-dependant and keep increasing due to multiple paths Page 24 In a typical high-speed system.
16、 Badly routed traces in packages and boards are the culprits of generating EMI and high-speed connectors tend to amplify the EMI problems. Page 25 Connectors High-speed traces Minimizing EMI on Packages and Boards greatly minimized System EMI problem. Example #5: Impact of Shielding for FX-Graphics
17、card Goals: - Confirm Emission from high-speed board - What-if analysis for low-cost suppression material - Metal Shield - R4N Suppression material (from NEC) Page 26 Far-Field Radiation of TMDS Signals Page 27 Analysis 770MHz Confirm Max radiation Bottom of brd due to TMDS routing: Max Angle: 144/1
18、60 26uWatts Total-PWR Antenna-Gain is -48dB 5uWatts/Steradian Metal Shield Mounted on Bottom of the Card Page 28 Metal Shield Metal-Shield Mounting on bottom of PCB connected to heat-sink screws No Major Change of Radiation Field Total Power increased slightly 27uWatts Max Radiation Bottom of PCB (1
19、57/161) Intensity increased slightly: 6uWatts/Steradian Antenna-Gain -47dB (worse) R4N Mounted on Bottom of the Card Page 29 Suppression Material R4N Material placed on Bottom of the PCB Major improvement of Radiation field from bottom of PCB: Total PWR dropped to 13uWatts (50%) Antenna-Gain dropped to -51.5dB (3dB) Intensity dropped to 2uWatts/Steradian (60%) Comparison of Radiation from Bottom of PCB with/Without R4N Suppression Material Page 30 R4N Material reduces the EMI radiation of TMDS signals especially from Bottom of the PCB
