1、1. Shown below is a level restore circuit of pass transistor. (1) Without transistor Mr, verify by using HSPICE and TSMC 0.18 um CMOS technology model with 1.8 V power supply that the high input to the signal- restoring inverter only charges up to VDD - VTn.(2) After inserting Mr, verify that the hi
2、gh input to the signal-restoring inverter can charge up to VDD.Solution：（1）不带电平恢复管的代码：.title LEVEL NO RESTROE .lib C:synopsysHspice_D-2010.03-SP1tsmc018mm018.l TT * set 0.18um library.options post=2 list.temp 27.global vdd Vdd vdd gnd 1.8vin vin 0 0.9 pulse 0.0 1.8 250p 5p 5p 490p 1000p*C1 2 gnd 0.0
3、1f.subckt no-restore A s1 wn=0.4u t=0.75umn A vdd s1 gnd NCH l=0.2u w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*t.ends.subckt inv in out wn=0.4u wp=1.2u t=0.75um1 out in gnd gnd NCH l=0.2u w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tm2 out in vdd vdd PCH l=0.2u w=wp ad=wp*t pd=wp+2*t as=wp*t ps=wp+2*t.endsX1
4、 vin x no-restore X2 x vout inv .op.tran 5p 4000p.meas tran voutmax max v(x) from=50p to=4000p.meas tran voutmin min v(x) from=50p to=4000p.meas tran tphl+trig v(vin) +val=0.9 +rise=2+targ v(vout) +val=0.5*(voutmax-voutmin)+voutmin +fall=2.meas tran tplh+trig v(vin) +val=0.9 +fall=2+targ v(vout) +va
5、l=0.5*(voutmax-voutmin)+voutmin +rise=2.print dc v(vin) v(vout) v(x).end（2）带电平恢复管的代码：.title LEVEL RESTROE .lib C:synopsysHspice_D-2010.03-SP1tsmc018mm018.l TT * set 0.18um library.options post=2 list.temp 27.global vdd Vdd vdd gnd 1.8vin vin 0 0.9 pulse 0.0 1.8 250p 5p 5p 490p 1000p*C1 x gnd 0.01f.s
6、ubckt restore A s1 out wn=0.4u wp=1u t=0.75umn A vdd s1 gnd NCH l=0.2u w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tmr s1 out vdd vdd PCH l=0.2u w=wp ad=wp*t pd=wp+2*t as=wp*t ps=wp+2*t.ends.subckt inv in out wn=0.4u wp=1.2u t=0.75um1 out in gnd gnd NCH l=0.2u w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tm2 o
7、ut in vdd vdd PCH l=0.2u w=wp ad=wp*t pd=wp+2*t as=wp*t ps=wp+2*t.endsX1 vin x vout restore X2 x vout inv .op.tran 5p 4000p.meas tran voutmax max v(x) from=50p to=4000p.meas tran voutmin min v(x) from=50p to=4000p.meas tran tphl+trig v(vin) +val=0.9 +rise=2+targ v(vout) +val=0.5*(voutmax-voutmin)+vo
8、utmin +fall=2.meas tran tplh+trig v(vin) +val=0.9 +fall=2+targ v(vout) +val=0.5*(voutmax-voutmin)+voutmin +rise=2.print dc v(vin) v(vout) v(x).end二者分析如下不带电平恢复管的测量数据：带电平恢复管的测量数据：得到的电压波形如下：上方的波形为加入电平恢复管，下方为未加入电平恢复管。根据测量数据可知道：未加入电平恢复管最大 v(x)=1.1446，加入电平恢复管v(x)=1.8003，但是根据延时数据和图像可以知道加入电平恢复管延时增加，但是对称性变好了
9、，同时上方图像的 v(x)的图形有一个弯曲，经过实验可以知道这个弯曲和 x 点的电容值有关。2. Figure 2-1 shows a cascade of dynamic n-type inverters and Figure 2-2 a cascade of domino logic of inverters. (1) Verify by HSPICE that the straightforward cascading of dynamic gates to create more complex structures (Figure 2-1) does not work. (2) Ve
10、rify by HSPICE that the cascade of domino logic of inverters (Figure 2-2) works.Figure 2-1Figure 2-2Solution：（1）、串联 N 型动态门代码如下：.title N-TYPE INV .lib C:synopsysHspice_D-2010.03-SP1tsmc018mm018.l TT * set 0.18um library.options post=2 list.temp 27.global vdd Vdd vdd gnd 1.8vclk vclk 0 0.9 pulse 0.0 1
11、.8 250p 5p 5p 490p 1000pvin vin 0 0.9 PWL 0p 0,150p 0,155p 1.8*C1 x gnd 0.01f.subckt N-TYPE-INV clk in out wn=0.4u wp=1.2u t=0.75umn d1 clk gnd gnd NCH l=0.2u w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tmin out in d1 gnd NCH l=0.2u w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tmp out clk vdd vdd PCH l=0.2u w=
12、wp ad=wp*t pd=wp+2*t as=wp*t ps=wp+2*t.endsX1 vclk vin out1 N-TYPE-INV X2 vclk out1 out2 N-TYPE-INV .op.tran 5p 2000p.meas tran out1max max v(out1) from=50p to=2000p.meas tran out1min min v(out1) from=50p to=2000p.meas tran out2max max v(out2) from=50p to=2000p.meas tran out2min min v(out2) from=50p
13、 to=2000p.print dc v(vclk) v(vin) v(out1) v(out2).end得到测量数据如下：波形图如下：从测量数据和波形图可以看出 out1 下降到 VTn 以下之后，out2 停留在中间电平电平约为 1.0V，因为毛刺的原因使整个电路的最大电压和最小电压偏高和偏低。所以整个电路不能正常工作。（2）、多米诺反相器逻辑代码如下：.title DOMINO LOGIC OF INVERTERS.lib C:synopsysHspice_D-2010.03-SP1tsmc018mm018.l TT * set 0.18um library.options post=2
14、 list.temp 27.global vdd Vdd vdd gnd 1.8vclk vclk 0 0.9 pulse 0.0 1.8 250p 5p 5p 490p 1000pvin vin 0 0.9 PWL 0p 0,400p 0,405p 1.8,550p 1.8,555p 0*C1 x gnd 0.01f.subckt N-TYPE-INV clk in out wn=0.4u wp=1.2u t=0.75umn d1 clk gnd gnd NCH l=0.2u w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tmin out in d1 gnd
15、NCH l=0.2u w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tmp out clk vdd vdd PCH l=0.2u w=wp ad=wp*t pd=wp+2*t as=wp*t ps=wp+2*t.ends.subckt inv in out wn=0.4u wp=1.2u t=0.75um1 out in gnd gnd NCH l=0.2u w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tm2 out in vdd vdd PCH l=0.2u w=wp ad=wp*t pd=wp+2*t as=wp*t ps=
16、wp+2*t.endsX1 vclk vin out-1 N-TYPE-INVX2 out-1 out1 inv X3 vclk out1 out-2 N-TYPE-INV X4 out-2 out2 inv.op.tran 5p 2000p.meas tran out1max max v(out1) from=50p to=2000p.meas tran out1min min v(out1) from=50p to=2000p.meas tran out2max max v(out2) from=50p to=2000p.meas tran out2min min v(out2) from
17、=50p to=2000p.meas tran tplh+trig v(out1) +val=0.5*(out1max-out1min)+out1min +rise=1+targ v(out2) +val=0.5*(out2max-out2min)+out2min +rise=1.meas tran tphl+trig v(out1) +val=0.5*(out1max-out1min)+out1min +fall=1+targ v(out2) +val=0.5*(out2max-out1min)+out2min +fall=1.print dc v(vclk) v(vin) v(out1)
18、v(out2).end得到测量数据如下：得到波形如下图：分析如下：在预充电期间 N 型动态门被充电到 VDD 而反相器输出 out1 则置 0，在求值期间（即 CLK 为高电平期间）动态门因为 Vin 从 01 的翻转而使得输出反相器输出 out1 也是 01，从而第二级输出 out2 也是 01，代表着第一级的多米诺逻辑的输入传递到了第二级的输出，多级也是如此，同时求值期间Vin 从 10 变化的变化不能影响整体的输出，只有在 CLK 由 10 期间发生改变，符合整个求值期间只有 01 翻转的多米诺逻辑设计规则。同时整个电路毛刺相比于 N 型动态门来说毛刺减小，因此提高了抗噪声的能力。根据上图和测量的数据还可以看出 out1、out2 的 tplh 有一定延时为 78ps，而tphl 相对来说基本为 0 为 3.6ps。
