1、1,P32 1-4,Draw a logic diagram for a full-adder .Name each logic gate.Draw a four-bit adder as a type.Draw the component is repeated,you can draw its sub-components once and refer to them elsewhere in the diagram.,2,P32 1-4 题目要求,(1)画出1位全加器的逻辑图 (2)给每一个逻辑门命名 (3) 由四个一位加器组成一个四位全加器 (4) 给四位全加器中的每一个器件命名 (5
2、) 画出器件层次化图（从四位全加器到逻辑门， 如有重复可在图上标注参考其它器件）,3,1位全加器真值表,4,逻辑表达式,5,1bit full adder schematic,6,4bit full adder schematic,A3 B3,A2 B2,A1 B1,A0 B0,cin,cout,Sum0,Sum1,Sum2,Sum3,a0,a1,a2,a3,7,A component hierarchy,4bit adder,a0,a1,a2,a3,n1,n2,x2,x1,n3,n4,identical to a0s subcells,8,p98 2-1,Draw the cross-sec
3、tion of the inverter shown below along a cut through the middle of the p-type and n-type transistors.,9,P98 2-1,P-tub,N-tub,n+,n+,p+,p+,poly,oxide,substrate,p-,n-,10,P98 2-2a,VdsVgsVt Linear region:IdKW/L(VgsVt)Vds0.5Vds2VdsVgsVt Saturation region: Id0.5KW/L(VgsVt) 2 From Table 2-4 Kn73A/V2 Vtn0.7V
4、VgsVt 3.30.72.6 (V) Vds=1V, 2V is linear region Vds=3.3V, 5V is saturation region,a)W/L5/2,Assuming that Vgs=3.3V,compute the drain current through n-type transistors of these sizes at Vds values of 1v,2V,3.3V,and 5V:,11,P98 2-2b-c,b)W/L8/2,c)W/L12/2,12,P98 2-2d,d)W/L25/2,13,P99 2-5,Justify(证明是正当的)
5、each of these design rules: 2 poly-poly spacing Prevents shorting of two poly wires b) No required poly-metal spacing Metal and poly are on different layers, so they will not touch if their geometries overlap c) 1 of diffusion and metal surrounding cut; Must make sure that metal fully covers the cut
6、 to ensure a lowresistance connection. Must also make sure that the via contacts only diffusion, not any of the tub surrounding the diffusion. d) 2 overhang of poly at transistor gate. Must make sure that the poly completely disconnects the source and drain regions, otherwise the transistor will be
7、shorted by a diffusion trace.,14,P99 2-6,Explain Why is ndiff-to-pdiff spacing so large? Ndiff and pdiff are in the different tub.The tub boundary represents a large change in doping, which cant be performed in a small area. b) Why is metal-metal spacing larger than poly-poly spacing? Because metal
8、is placed on after poly, there is more variation in the surface that the metal is placed on, therefore more possibility of shorting, thus the greater metal-metal spacing requirement. c) Why is metal2-metal2 spacing larger than metal1-metal1 spacing? Because metal2 is placed on after metal1, there is
9、 more variation in the surface that the metal2 is placed on, therefore more possibility of shorting, thus the greater metal2-metal2 spacing requirement.,15,P99 2-7,What distinguishes a tub tie from an ndiff-metal1 via?A tub tie connects to the tub and includes an extra diffusion of the same type as
10、the tub. For example,the tub tie next to the ndiff-metal1 via would use a p+ diffusion to connect to the tub.,16,P99 2-9,Compute the resistance and capacitance for each polysilicon wire below: a)Assume 1=0.25m Area=3.75m0.5m=1.875m2 Perimeter=3.75m2+0.5m2=8.5m P80 Table 2-4: C=0.09fF/m21.875m2+0.04
11、fF/m8.5m=0.51 fF R=4/7.5=30,15,2,17,P99 2-9,Compute the resistance and capacitance for each polysilicon wire below: b)Assume 1=0.25m Area=3.75m0.5m2+1m0.5m =4.25m2 Perimeter=3.75m2+3.25m2+0.5m2+1m+2m=18m C=0.09fF/m24.25m2+0.04 fF/m18m =1.1 fF R=4/6.52+4/2+4/1=64,15,2,2,4,18,P99 2-10,Compute the para
12、sitic resistance and capacitance of the source/drain region of transistors of the types and sizes given below,assuming that these source drain-regions have the required 3 overhang past the gate: a)p-type;W/L=3/2;b)n-type;W/L=4/2;c)p-type;W/L=6/2;d)n-type;W/L=12/2;,19,P99 2-10a,Use P80 table 2-4 Typi
13、cal parameters for 0.5um process: =0.25 , 3=0.75, a)p-type;W/L=3/2=0.75/0.5 perimeter: (0.75+0.75)2=3um area:0.75 0.75=0.5625um2 Cpdiff,bot = 0.9fF/ m2 Cpdiff,side =0.3fF/ m Rpdiff = 2 / Ctotal= 0.9 0.5625+ 0.3 3=1.4fF R= 2 ,20,P100 2-10b,Use P80 table 2-4 Typical parameters for 0.5um process: =0.25
14、 , 3=0.75, a)n-type;W/L=4/2=1/0.5 perimeter: (0.75+1)2=3.5um area:0.75 1=0.75um2 Cndiff,bot = 0.6fF/ m2 Cndiff,side =0.2fF/ m Rndiff = 2 / Ctotal= 0.6 0.75+ 0.2 3.5=1.2fF R= 2 0.75=1.5 ,21,P100 2-10c,Use P80 table 2-4 Typical parameters for 0.5um process: =0.25 , 3=0.75, a)p-type;W/L=6/2=1.5/0.5 per
15、imeter: (1.5+0.75)2=4.5um area:0.75 1.5=1.1um2 Cpdiff,bot = 0.9fF/ m2 Cpdiff,side =0.3fF/ m Rpdiff = 2 / Ctotal= 0.9 1.1+ 0.3 4.5=2.3fF R= 2 0. 5=1,22,P100 2-10d,Use P80 table 2-4 Typical parameters for 0.5um process: =0.25 , 3=0.75, a)n-type;W/L=12/2=3/0.5 perimeter: (0.75+3)2=7.5um area:0.75 3=2.2
16、5um2 Cndiff,bot = 0.6fF/ m2 Cndiff,side =0.2fF/ m Rndiff = 2 / Ctotal= 0.2 7.5+ 0.6 2.25=2.85fF R= 2 (0.753)=0.5 ,23,P101 2-13,Reverse-engineer the layout shown on next page.Draw: a stick diagram corresponding to the layout; a transistor schematic. Label inputs and outputs in your drawings in accord
17、ance(一致) with the labels in the layout.,N,in,out,VDD,VSS,24,2-13 a stick diagram,D,Vdd,Vss,in,out,N,25,2-13 A transistor-level schematic,in,out,N,26,P103 2-19,Design a layout for the circuit shown below in two stages:first draw a stick diagram, then design the complete layout. Assume that all transi
18、stors are 3/2. The power supply lines should run through the cell in metal1, available on opposite side of the cell.,i1,i2,out,out,VDD,VSS,i1,i2,a stick diagram,27,P103 2-19 layout,28,P171 3-1,Design the static complementary pullup and pulldown networks for these logic expressions: a) (a+b+c) b) (a+
19、b)c c) (a+b)(c+d),a,b,29,c) (a+b)(c+d),=,(a+b)(c+d),a,a,b,b,c,c,d,d,out,30,P171 3-2a,Write the defining logic equation and transistor topology for each complex gate below: a) AOI-22 b) OAI-22 c) AOI-212 d) OAI-321 e) AOI-2222,a) AOI-22:(ab+cd),a,a,b,b,c,c,d,d,out,31,b) OAI-22:(a+b)(c+d),a,a,b,b,c,c,
20、d,d,out,c) AOI-212:ab+ c+de,a,a,b,b,c,c,d,d,out,e,e,32,d,e,e) AOI-2222(ab+cd+ef+gh),a,b,b,a,c,c,d,d,e,e,f,f,out,a,b,b,a,c,c,d,d,e,e,f,f,out,g,g,h,h,33,P172 3-9,Design a three-input, static complementary NAND gate, which implements this function,Draw a switch-level schematic Draw a stick diagram,34,b
21、) Draw a stick diagram,a) Draw a switch-level schematic,VDD,VSS,a,b,c,out,35,P173 3-10,Here is a partial schematic for a two-input XOR gate: The gates output is 1 when exactly one of its input is 1. The schematic is partial because transistors in the diagram require both the true(a) and complement(a
22、) form of the inputs, but the inverters which generate aand b from a and b are not shown. Write the truth table for the two-input XOR. Complete the schematic for this gate-compute the complement of the inputs using inverters. Draw a stick diagram for the partial XOR schematic. Draw a stick diagram f
23、or the complete XOR schematic,36,a)Write the truth table for the two-input XOR.,a,a,a,b,b,a,b,b,out,37,b) Complete the schematic for this gate-compute the complement of the inputs using inverters.,b,38,c)Draw a stick diagram for the partial XOR schematic.,VDD,VSS,out,b,a,a,b,a,a,b,b,a,b,b,a,39,d) Dr
24、aw a stick diagram for the complete XOR schematic.,VDD,VSS,out,b,a,a,b,a,b,b,a,a,b,40,P174 3-15,Draw the circuit topology of a three-input NOR gate designed in pseudo-nMOS.,41,P174 3-16,Design a two-input AND gate in domino logic: a)Draw a transistor schematic b)Draw a stick diagram,a,b,out,a),a,b,o
25、ut,42,P236 4-1,If we route horizontal tracks in metal 1 and vertical tracks in metal 2,what are the horizontal and vertical grid spacings for channels in our SCMOS process?,The spacing between horizontal wires is 6.5 The spacing between vertical wires is 7.5 (reference P7778 SCMOS design rules ) The
26、 distance between tracks is equal to the minimum spacing between a wire and a via,43,P236-237 4-2答案,This channel cannot be routed using the left edge algorithm because pins C and F are vertically aligned making it impossible to route the channel with single horizontal tracks.Doglegging is required t
27、o successfully route this channel.,C,A,G,F,D,F,A,D,B,A,G,E,C,B,G,E,F,44,P237 4-4 (a),a,b,c,d,0,5,10,b,c,a,d,Using the assumptions and techniques of Example 4-5,find minimum-crosstalk routings for these channels.Use the distances between terminals shown on the ruler.,Crosstalk=4,题目不够严格!,45,P237 4-4(b
28、),a,b,c,d,e,0,5,10,e,d,c,a,e,b,d,c,b,a,e,Crosstalk=5,46,P237 4-4(c),a,b,c,d,e,f,0,5,10,e,f,d,c,f,a,e,b,Crosstalk=8.5,f,e,b,a,d,c,47,P240 4-7,Give at least one test for stuck-at-0 and stuck-at-1 faults for each of these static gates: a)(a+b+c) b)(a+b)c) c)(a+b)(c+d),a)(a+b+c) stuck-at-0:a=b=c=0 stuck
29、-at-1:a=b=c=1,b)(a+b)c) stuck-at-0:a=b=c=0 stuck-at-1:a=b=c=1,c)(a+b)(c+d) stuck-at-0:a=b=c=d=1 stuck-at-1:a=b=c=d=0,48,5-4 Draw a circuit diagram for a D-type master-slave flip-flop with a clear input based on the circuit of Figure 5-11(asynchronism),D,Q,clear,49,5-5 Draw a circuit diagram for a T-
30、type master-slave flip-flop based on the circuit of Figure 5-12,S,R,Q,Qbar,50,RS、T触发器 真值表,S=TQn R= TQn,51,由RS构成的T触发器逻辑图,S,R,Q,Qbar,T,52,由RS构成的T触发器分析,Q,Qbar,T,T,Q,Qbar,1,1,1,0,Q,Qbar,T,T,Qbar,1,0,1,0,Qbar,0,1,1,1,保持,竞争,0,0,1,保持,53,5-10 Write the state transition table for an three-bit conditional cou
31、nter.It has two inputs,count and reset(which returns the counter to the 0 counter),and a three-bit binary output of the current count.,54,5-10 state transition table,55,5-10 verilog hdl,module counter3(clk ,reset , count,out ); input clk,reset,count; output 2:0 out ; reg 2:0out ; always (posedge clk
32、)beginif (!reset)out = 0 ;else if (count)out = out + 1 ;end endmodule,56,5-10 waveform,57,5-10 state transition graph,out=000,out=001,out=111,out=110,out=101,out=100,out=011,out=010,58,5-15 Draw a transistor schematic for a master-slave(D-type) flip-flop built from clocked inverters.,in,out,p1,n1,sy
33、mbol,circuit,59,5-15答案,D,Q,master,slave,60,6-9(p345),Consider an ALU design: a)Enumerate all the 16 possible functions of a two-input ALU. b)For a-b,b-a,-a,-b list the control inputs to the three function blocks of the three function block ALU.,61,a)Enumerate all the 16 possible functions of a two-i
34、nput ALU.,62,a)Enumerate all the 16 possible functions of a two-input ALU.,63,b)For each possible function,list the control inputs to the three function blocks of the three function block ALU.,64,6-13(p345),Design components of a Booth multiplier: a)Design the logic for one bit of the adder-subtract
35、er. b) Design a stick diagram for your adder-subtracter.,65,6-13a)Design the logic for one bit of the adder-subtracter.,Assume that we use the control signal op=1sum, op=0difference,66,6-13一位加减法器逻辑图,67,6-13一位加减法器波形,68,6-13四位加减法器逻辑图,69,6-13四位加减法器波形,70,7-4 Can the floorplan below be routed with planar
36、 power and ground nets?If so,give a routing.If not,explain why.,VSS,VDD,VSS,VSS,VSS,VSS,VSS,VSS,VDD,VDD,VDD,VDD,VDD,VDD,VDD,VDD,VSS,VSS,This floorplan can be routed with global power and ground nets.The bifurcation lines on the cells show that VDD is always on the left side of the cell.,71,7-5 How m
37、uch current can be supplied by a 10m wide power line in a pad ring?,Assume that each micron of wire width can safely carry 1.5mA of current,So I=101.5mA=15mA,72,7-7 A chip core is 3000m2500m and requires 0.8A.It needs 18 signal input pads and 19 signal output pads. a)How many VDD and VSS pads are re
38、quired assuming a 12 m power ring?,Assume that each output pad requires 1.5mAof current;assume that each input requires1mA.The pads then require 46.5mA of current.That would require three VDD and three VSS pads .,b)Will the total chip size be limited by the chip core or by the pad ring?,There will b
39、e a total of 43 pads.If each pad is 200m on a side,the pads will require 8600 m of space around the ring.Therefore,the chip will be core-limited,not pad limited.,73,7-8 Why doesnt an output pad require electrostatic discharge protection circuitry?,An output pad is connected to a transistor source or
40、 drain and not to the transistor gate.Because the pad is not connected to the gate the thin gate oxide layer cannot be destroyed by a voltage spike.,74,8-4 Design an ASM chart for the traffic light controller of Example 5-4,highway=green farm=red,cars&long,reset=1,reset=0,N,Y,highway=yellow farm=red
41、,short,reset=1,reset=0,N,Y,highway= red farm= green,cars&long,reset=1,reset=0,N,Y,highway=red farm=yellow,short,reset=0,N,Y,reset=1,75,8-14 Schedule the dataflow graph of Figure 8-19 assuming that two additions can be chained in one clock cycle: a)show the ASAP schedule;,one cycle,76,8-14 b)show the
42、 ALAP schedule;,one cycle,77,9-2 Write a register-transfer description of the ones-seconds digit of a timer.,seconds=0,N,Y,Y,value=59,value=0,go,reset,value= value-1,incr,seconds,value= value+1,Y,N,Y,Y,N,N,N,78,9-4 Design the seven-segment decoding function: a)Write a truth table whose rows are the digits 0-9 and whose columns are the on signals for the seven segments.,79,9-4 b)Write seven Boolean functions,one for each segment,giving the segments on signal in terms of the BCD digits bits.,
