1、6.1 The Challenges for Physical Limitations in Si MicroelectronicsI. INTRODUCTION For the past four decades, the semiconductor industry has experienced exponential（指数的） progress, this is unique not only on its development speed, but also on its influence on the society and life of human being. 在过去的四
2、十年中，半导体工业经历了指数式的进步，这不仅仅是在发展速度上，而同时表现在对人类社会和生活的影响上自从 40 年前晶体管发明以来, 微电子技术无论是从其发展速度及对人类社会生产和生活的影响, 都可以说是科学技术史上空前的。The feature size of semiconductor devices are continued to scale down for higher integrated density, faster circuit speed and lower power dissipation（耗散）. 为了更高的集成度，更快的电路速度和更低的功耗，半导体器件的特征尺寸不
3、断的缩小。Currently the 0.25m CMOS technology has become the prevailing technology for VLSI applications.目前 0.25 微米的 CMOS 技术对于 VLSI 来说已经成为主流技术Meanwhile, 0.1m CMOS and 0.04m NMOS devices have recently been fabricated in research laboratories , and by the year 2010, the 64Gb DRAM will be expected to be fab
4、ricated with 0.07m lithography. 目前， 0.1 微米的 CMOS 和 0.4 微米的 NMOS 器件都已经在在实验室中制备成功，到 2010 年，64G 的 DRAM 将可望以 0.07 微米的光刻技术制造出来。Based on such a trend, some key questions on silicon microelectronics further development are: 基于这种趋势，硅微电子将来发展的主要问题是：What are the fundamental limitations of silicon microelectron
5、ics when（） scaling down? Are we approaching to the limits? What can we do facing to the limitations and the limits? 当尺寸下降以后，硅微电子技术的基本限制是什么？我们是否接近到了极限？面临的极根和限制，我们可以做些什么？6.1.2. THE CHALLENGES FOR PHYSICAL LIMITATIONS IN SI MICROELECTRONICS Since 1972, the limitations of Si MOSFET scaling down has bein
6、g researched widely, the predicted minimum feature size of MOSFET changed from 0.25m to 0.lm, but it was broken through every time, now the 0.04m has been fabricated successfully. 自 1972 年以来，(科学家们)对硅金属氧化物半导体场效应晶体管的极限尺寸进行了广泛的研究，对金属氧化物半导体场效应晶体管的最小形体尺寸预测从 0.25 微米变到 0.1 微米， 但是每一次预测都被打破了, 现在 0.04 微米的晶体管已
7、经成功制造出来。Originally the research of limitations were focused on the limitations of devices scaling down. 最初，对极限尺寸的研究集中在微电子技术方面However, as the microelectronics technology developed into 0.lm and beyond, the researches of limitations should be focused on the whole integrated system instead of only on t
8、he devices. 然而，随着微电子技术发展到 0.1 微米及以下，对极限尺寸的研究必须集中到整个集成系统而不是单个器件。And the new concepts, new method should be taken facing to the challenges of limitations. 要挑战极限，必须应用一种新的技术，新的方法。The future opportunities for microelectronics to achieve gigascale integration will be governed by a series of theoretical an
9、d practical limitation. 在微电子学方面要获得千兆规模的集成度将由一系列理论和实际限制所决定。These include: fundamental physical limits, material limitations, technology limitations, devices limitations, circuits and system limitations. 这包括：理论物理极限，材料限制，技术限制，器件限制，电路及系统限制。6.31 Introduction With growing complexities of digital devices t
10、he generation of a complete verification suite requires an ever increasing portion of the development time and resources. 随着数字设备的复杂化，制造完整的验证套件需要的开发时间和资源不断增加Today, even though extensive verification has been employed, devices with incorrect functional behaviour are occasionally manufactured and marke
11、ted. 今天，即使采用了更广泛的验证技术，带有功能缺陷的设备仍然被偶尔生产和销售Typically, the erroneous logical implementation has not been detected due to inappropriate verification criteria. 通常，错误的逻辑实现由于采用不适当的验证标准而没有被发现An important contributing factor to such oversights is that those preparing the test suite inadvertently tend to base
12、 it on anticipated device applications and therefore misinterpret the specification in the same way as the designers. 造成这样的疏忽的一个重要的因素那些准备检测套件的人不自觉（不注意的）的倾向于让检测基于预期的器件应用，由此以与设计者一样的方式曲解了说明（技术要求）。An example of this could be when an embedded microprocessor is verified by cosimulation with the target app
13、lication software.采用目标应用软件协同仿真技术对嵌入式微处理器进行验证就是一个这样的例子，Another contributing reason is that the verification bottleneck lays in the time spent on developing the test suite rather than simulating it (Ref. 1). 另一个产生原因是验证的瓶颈在于大部分时间花在了发展测试套件上而不是用于仿真We have approached these problems by stimuli（激励）generatio
14、n for microprocessors decoupled from the foreseen usage of the device. 我们采用激励生成技术将微处理器从器件的预期功能中分离出来以处理这类问题Our method relies on comparison of behaviour between different representations of the microprocessor. 我们的方法在于比较不同表示的微处理器的表现The notion of a valid software program is abandoned for the stimuli gen
15、eration, effectively resulting in a program-less verification approach for microprocessors. 对于激励生成而言，抛弃了一个有效软件的概念，有效的得到无程序的微处理器验证技术Additionally, limitations associated with software developments tools are eliminated in the stimuli generation process. 此外，消除了在激励生成过程中软件开发工具的相关限制The ratio between simula
16、tion time and testbench coding time is increased, allowing a larger number of errors to be found per time unit spent on stimuli development. 仿真时间和测试矢量的译码时间之比提高了，由此在每一个用于激励开发的时间段内都有可能发现大量的错误These characteristics yield in an acceleration of the overall verification process. 这一特点加速了整个验证过程。 For complex
17、designs it is necessary to obtain a correct reference model tha is used throughout the development. 对复杂的设计来说，必须要有一个在整个开发过程中使用的正确的参考模型。When describing a reference at a high abstraction level, the functionality is not obscured by implementation details which allows an easier understanding of the probl
18、em and reduces the possibility for introduction of errors. 在较高的抽象层描述参考模型时，参考模型的功能性在执行细节上必需是清晰的（不能是含糊的），由此才能轻易的理解问题并减少引入错误的概率。 By applying the same stimuli to the test object as to the reference model, errors can be detected by comparing the obtained results. 对测试对象和参考模型都采用同样的激励技术，通过比较获得的结果就可以检测出错误。Th
19、e testbench has to be able to adapt dynamically to the response from either model to tolerate（容忍） correct but dissimilar behaviour resulting from the models being at different abstraction levels. 测试矢量必需能够动态地适应任一模型的响应，以容忍模型在不同抽象层上的正确的但是表现不同的行为The stimuli is pseudo randomly generated and applied to th
20、e test object and the reference. 激励被伪随机产生并应用于测试对象和参考模型Existing methods employ generators coupled with assemblers and other software development tools, producing pseudo random software programs to be executed as stimuli. 现有的方式是采用发生器和汇编程序及其它的软件开发工具偶合，产生象激励一样被执行的的伪随机软件程序Such stimuli have some disadvant
21、ages since they have to adhere to the limitations that are attributed to a valid and executable program. 这样的激励有一些缺点，因为他们都带着属于有效和可执行的程序所具有的限制。Instead of relying on existing pseudo random generators and software tools we generate the stimuli during the actual simulation. 为了不依靠现有的伪随机发生器和软件工具,我们在实际模拟中产生
22、激励A microprocessor is simply seen as a state machine being fed with instructions and data which are conceived on the fly（ 动态 ）, effectively resulting in a program-less verification approach. 一片微处理器可以简单的看成一个状态机，加入动态生成的指令和数据，有效的产生一个无程序的验证方法。Any correlation between the specified function and its usage
23、is thus avoided by completely abandoning the notion of a program. 由于完全抛弃了程序的概念，所以避免了特定功能和其应用之间的任何相关性。To cope with different abstraction levels and to allow program-less verification, we have chosen to develop the complete testbench in VHDL. 为了处理不同的抽象级和允许无程序验证，我们选择在 VHDL 中开发完全的测试平台The testbench inclu
24、des the reference model and the test object, and pseudo random generation of executed instruction and data sequences. 测试平台包括参考模型和测试目标和伪随机生成的执行指令和数据序列 Today, testbench development is more time consuming than the actual simulation. 今天，测试平台的开发比实际仿真更花时间。Methods increasing the simulation portion of the t
25、ime spent on verification are therefore becoming attractive. 由此，可提高验证中仿真所占的时间比例的方法更具吸引力。The outlined approach offers an acceleration of the verification process by reducing the effort required for the definition and implementation of a stimuli for finding a given number of errors. 概述法在寻找一定数量的错误时可以减少
26、在定义和执行一个激励所花费的时间，所以可以加速验证过程。This paper starts with an overview of different functional verification approaches. 本文首先回顾了不同的功能验证方法。It is followed by a presentation of our method and an in-depth description of how it was applied to a real project. 随后叙述我们的方法并深入描述（这种方法）如何应用于实际项目。Some relevant cases are t
27、hen discussed. Finally, the conclusions from the experience are drawn. 同时讨论了相关的案例，最后从实际经验中得出结论6.3.2 Current verification approaches 现有的验证方法6.3.2.1 Manual stimuli and inspection 手动激励和检查In the past when designs were small, tests were conceived manually. 在过去，因为设计很小，所以测试都是手工进行的。For the stimuli, the simu
28、lator was commanded directly in front of the workstation, and the response in the form of waveforms was visually inspected on the screen. 对于激励来说， 模拟器在工作站前方执行命令，并且以波形的形式反馈在屏幕供上观察Depending on the response, subsequent stimuli were conceived in an interactive manner. 根据此响应，以交互式的方式设想下一激励。For example, if
29、an error was detected, its effect on the verification could be reduced by avoiding to exercise that part of the design until the error had been corrected. 如果检测到一个错误，在其改正之前通过避免执行那一部分设计就可以减少验证While this approach is manageable for small designs, its drawbacks include: 然而这种方法只适用于小型设计，其缺点包括： risk for con
30、fusing the actual behaviour as seen on the screen with what has been specified, especially when under pressure to complete the work; 特别是在尽快完成工作的压力下，可能有混淆在屏幕上反映出来的实际表现和指定功能的风险 limited length of the verification since requiring the person to be present at the workstation while simulating; 由于模拟时要有人在场，验
31、证的时间有限 unsuitable for repeatable regression testing （回归测试）since interactive, and furthermore the quality of repeated simulations varies with the day-to-day performance of the person running it. 不适合重复的回归测试，由于是交互式的，而且重复模拟质量随着操作人员日复一日的表现而变化6.3.2.3 Automated testbenches 自动验证With the introduction of hard
32、ware description languages, the designer was not only provided with a powerful tool for describing the design itself, but also with a tool highly suitable for verification. 随着硬件描述语言的引入，设计师不仅仅是获得了一个有力的设计描述工具，同时还获得非常适合的验证工具The concept of testbenches was introduced, comprising stimuli generators and ch
33、eckers for functional correctness.包含了激励发生器和功能检验器的 测试平台概念被引入. The correctness checkers can be devised in ways allowing different, although correct, responses from different implementations or representations of a design under test功能检验器可以设计成可允许不同但正确的响应，这响应来自于被检测的设计的不同实现和表征With checkers that abstract f
34、rom implementation details and concentrate on functionality, verification at a higher abstraction level is made possible. 由于检验器对执行细节进行抽象和功能浓缩，就使得高抽象层的验证变得可行。An example of how verification is performed at a higher abstraction level is when a checker comprises a bit-serial receiver that outputs the re
35、ceived data for further processing. 举一个高抽象层如何实现验证的例子，当一个含有位串行接收器的检验器为下一过程输出接收到的数据时，A higher level checker can then analyse the received data without involving any implementation details of the communication protocol（协议） in the process. 高层检验器可以随后分析接收到的数据而不涉及在整个过程中通信协议的任何执行细节The checker is thus not bo
36、und by cycle or waveform-true comparison and can therefore accept low-level deviations. 检验器就不会被束缚于周期和波形校验上，由此可以接受低层偏差When cycle-true comparison is desired, as for regressive verification, the testbench can be complemented with signature generators and checkers based on multiple input serial registers. 当需要周期校验时，如对于回归验证，测试平台可以由基于多重输入串行寄存器的信号发生器和检验器补充。
