1、 High Isolation,Silicon SPDT,Nonrefective Switch,9 kHz to 13.0 GHz Data Sheet HMC1118 Rev.0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable.However,no responsibility is assumed by Analog Devices for its use,nor for any infringements of patents or oth
2、er rights of third parties that may result from its use.Specifications subject to change without notice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.Trademarks and registered trademarks are the property of their respective owners.One Technolog
3、y Way,P.O.Box 9106,Norwood,MA 02062-9106,U.S.A.Tel:781.329.4700 2015 Analog Devices,Inc.All rights reserved.Technical Support FEATURES Nonreflective 50 design Positive control:0 V/3.3 V Low insertion loss:0.68 dB at 8.0 GHz High isolation:48 dB at 8.0 GHz High power handling 35 dBm through path 27 d
4、Bm terminated path High linearity 1 dB compression(P1dB):37 dBm typical Input third-order intercept(IIP3):62 dBm typical ESD rating:2 kV human body model(HBM)3 mm 3 mm,16-lead LFCSP package No low frequency spurious Settling time(0.05 dB margin of final RFOUT):7.5 s APPLICATIONS Test instrumentation
5、 Microwave radios and very small aperture terminals(VSATs)Military radios,radars,and electronic counter measures(ECMs)Fiber optics and broadband telecommunications FUNCTIONAL BLOCK DIAGRAM 1234GNDGNDRFCGND1211109VDDLSVCTRLVSS5678GNDGNDRF2GND16151413GNDGNDRF1GND5050PACKAGEBASEGNDHMC111812961-001 Figu
6、re 1.GENERAL DESCRIPTION The HMC1118 is a general-purpose,broadband,nonreflective single-pole,double-throw(SPDT)switch in a LFCSP surface mount package.Covering the 9 kHz to 13.0 GHz range,the switch offers high isolation and low insertion loss.The switch features 48 dB isolation,0.68 dB insertion l
7、oss up to 8.0 GHz,and a 7.5 s settling time of 0.05 dB margin of final RFOUT.The switch operates using positive control voltage logic lines of+3.3 V and 0 V and requires+3.3 V and 2.5 V supplies.The HMC1118 can cover the same operating frequency range with a single positive supply voltage applied an
8、d the negative supply voltage(VSS)tied to ground and still maintaining good power handling performance.The HMC1118 is packaged in a 3 mm 3 mm,surface mount LFCSP package.HMC1118 Data Sheet Rev.0|Page 2 of 11 TABLE OF CONTENTS Features.1A pplications.1Functional Block Diagram.1General Description.1Re
9、vision History.2S pecif ica t io ns.3Electrical Specifications.3Digital Control Voltages.4Bias and Supply Current.4Absolute Maximum Ratings.5ESD Caution.5Pin Configuration and Function Descriptions.6Interface Schematics.6Typical Performance Characteristics.7Insertion Loss,Return Loss,and Isolation.7
10、Input Compression Point and Input Third-Order Intercept.8Theory of Operation.9Applications Information.10Evaluation PCB.10Outline Dimensions.11Ordering Guide.11 REVISION HISTORY 10/15Revision 0:Initial Version Data Sheet HMC1118 Rev.0|Page 3 of 11 SPECIFICATIONS ELECTRICAL SPECIFICATIONS VCTRL=0 V/3
11、.3 V dc,VDD=LS=3.3 V dc,VSS=2.5 V dc,TA=25C,50 system,unless otherwise specified.Table 1.Parameter Test Conditions/Comments Min Typ Max Unit INSERTION LOSS 9 kHz to 3.0 GHz 0.5 1.0 dB 9 kHz to 8.0 GHz 0.68 1.1 dB 9 kHz to 10.0 GHz 0.7 1.3 dB 9 kHz to 13.0 GHz 1.3 2.0 dB ISOLATION RFC TO RF1/RF2(WORS
12、T CASE)9 kHz to 3.0 GHz 40 50 dB 9 kHz to 8.0 GHz 42 48 dB 9 kHz to 10.0 GHz 28 35 dB 9 kHz to 13.0 GHz 18 25 dB RETURN LOSS On State 9 kHz to 3.0 GHz 26 dB 9 kHz to 8.0 GHz 22 dB 9 kHz to 13.0 GHz 9 dB Off State 9 kHz to 3.0 GHz 26 dB 9 kHz to 8.0 GHz 14 dB 9 kHz to 13.0 GHz 5 dB RADIO FREQUENCY(RF
13、)SETTLING TIME 50%VCTRL to 0.05 dB margin of final RFOUT 7.5 s 50%VCTRL to 0.1 dB margin of final RFOUT 6 s SWITCHING SPEED tRISE/tFALL 10%/90%RF 0.85 s tON/tOFF 50%VCTRL to 10%/90%RF 2.7 s INPUT POWER 1 MHz to 13.0 GHz 1 dB Compression(P1dB)35 37 dBm 0.1 dB Compression(P0.1dB)35 dBm INPUT THIRD-ORD
14、ER INTERCEPT(IIP3)Two-tone input power=14 dBm at each tone,1 MHz to 13.0 GHz 62 dBm RECOMMENDED OPERATING CONDITIONS1 Positive Supply Voltage(VDD)3.0 3.6 V Negative Supply Voltage(VSS)2.75 2.25 V Control Voltage(VCTRL)Range 0 VDD V Logic Select(LS)Voltage Range 0 VDD V RF Input Power VDD/VCTRL=3.3 V
15、,VSS=2.5 V,TA=85C,frequency=2 GHz Through Path 35 dBm Termination Path 27 dBm Hot Switch Power Level VDD=3.3 V,TA=85C,frequency=2 GHz 27 dBm Case Temperature Range(TCASE)40+85 C 1 These are the recommended values for these parameters.HMC1118 Data Sheet Rev.0|Page 4 of 11 DIGITAL CONTROL VOLTAGES VDD
16、=3.3 V 10%,VSS=2.5 V 10%,TCASE=40C to+85C,unless otherwise specified.Table 2.Parameter Symbol Min Typ Max Unit Test Condition/Comments INPUT CONTROL VOLTAGE 1 A typical Low VIL 0.3+0.8 V High VIH 2.0 VDD+0.3 V BIAS AND SUPPLY CURRENT Table 3.Parameter Symbol Min Typ Max Unit SUPPLY CURRENT VDD=3.3 V
17、 IDD 20 200 A VSS=2.5 V ISS 0.5 10 A Data Sheet HMC1118 Rev.0|Page 5 of 11 ABSOLUTE MAXIMUM RATINGS Table 4.Parameter Rating Positive Supply Voltage(VDD)Range 0.3 V to+3.7 V dc Negative Supply Voltage(VSS)Range 2.8 V to+0.3 V Control Voltage(VCTRL)Range 0.3 V to VDD+0.3 V Logic Select(LS)Voltage Ran
18、ge 0.3 V to VDD+0.3 V RF Input Power1(V DD/VCTRL=3.3 V,VSS=2.5 V,TA=85C,Frequency=2 GHz)See Figure 2 to Figure 4 Through Path 37 dBm Termination Path 28 dBm Hot Switch Power Level(VDD=3.3 V,TA=85C,Frequency=2 GHz)30 dBm Storage Temperature Range 65C to+150C Maximum Reflow Temperature(MSL3 Rating)260
19、C Channel T emperature 135C Thermal Resistance(Channel to Package Bottom)Through Path 116C/W Terminated Path 100C/W ESD Sensitivity(HBM),Class 2 2 kV 1 For recommended operating conditions,see Table 1.Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the
20、product.This is a stress rating only;functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied.Operation beyond the maximum operating conditions for extended periods may affect product reliability.424201
21、6128400 10 9 8 7 6 5 4 3 2 1POWER(dB)FREQUENCY(GHz)12961-002 Figure 2.Power Derating Through Path 4242016128400.01 0.1 1 10 100 1000POWER(dB)FREQUENCY(MHz)12961-004 Figure 3.Power Derating Through Path(Low Frequency Detail)4242016128400.01 0.1 1 10 100 1000 10000POWER(dB)FREQUENCY(MHz)12961-003 Figu
22、re 4.Power Derating for Hot Switching Power ESD CAUTION HMC1118 Data Sheet Rev.0|Page 6 of 11 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1234GNDGNDRFCGND1211109VDDLSVCTRLVSS5678GNDGNDRF2GND16151413GNDGNDRF1GNDHMC1118TOP VIEW(Not to Scale)12961-005NOTES1.THE EXPOSED PAD MUST BE CONNECTEDTO THE RF/DC
23、 GROUND OF THE PRINTED CIRCUIT BOARD(PCB).Figure 5.Pin Configuration Table 5.Pin Function Descriptions Pin No.Mnemonic Description 1,2,4 to 6,8,13,15,16 GND Ground.The package bottom has an exposed metal pad that must connect to the printed circuit board(PCB)RF/dc ground.See Figure 6 for the GND int
24、erface schematic.3 RFC RF Common Port.This pin is dc-coupled and matched to 50.A dc blocking capacitor is required if the RF line potential is not equal to 0 V dc.7 RF2 RF2 Port.This pin is dc-coupled and matched to 50.A dc blocking capacitor is required if the RF line potential is not equal to 0 V
25、dc.14 RF1 RF1 Port.This pin is dc-coupled and matched to 50.A dc blocking capacitor is required if the RF line potential is not equal to 0 V dc.9 VSS Negative Supply Voltage Pin.10 VCTRL Control Input Pin.See Table 1,Table 2,and Table 6.11 LS Logic Select Input Pin.See Table 1,Table 2,and Table 6.12
26、 VDD Positive Supply Voltage Pin.EPAD Exposed Pad.The exposed pad must be connected to the RF/dc ground of the printed circuit board(PCB).Table 6.Truth Table Control Input Signal Path State LS VCTRL RFC to RF1 RFC to RF2 High Low On Off High High Off On Low Low Off On Low High On Off INTERFACE SCHEM
27、ATICS GND12961-006 Figure 6.GND Interface Schematic VDD12961-007VCTRL Figure 7.V CTRL Interface Schematic VDD12961-008LS Figure 8.LS Interface Schematic Data Sheet HMC1118 Rev.0|Page 7 of 11 TYPICAL PERFORMANCE CHARACTERISTICS INSERTION LOSS,RETURN LOSS,AND ISOLATION 043210 2 4 6 8 10 12 14INSERTION
28、 LOSS(dB)FREQUENCY(GHz)TA=40CTA=+25CTA=+85C12961-009 Figure 9.Insertion Loss vs.Frequency 050403020100 2 4 6 8 10 12 14RETURN LOSS(dB)FREQUENCY(GHz)RF1,RF2 OFFRFCRF1,RF2 ON12961-011 Figure 10.Return Loss vs.Frequency 09080706050403020100 2 4 6 8 10 12 14ISOLATION(dB)FREQUENCY(GHz)RF1RF212961-010 Fig
29、ure 11.Isolation Between RFC and the RF1 and RF2 Ports vs.Frequency 01009080706050403020100 2 4 6 8 10 12 14ISOLATION(dB)FREQUENCY(GHz)RFC TO RF1 ONRFC TO RF2 ON12961-012 Figure 12.Isolation Between RF1 and RF2 Ports vs.Frequency HMC1118 Data Sheet Rev.0|Page 8 of 11 INPUT COMPRESSION POINT AND INPU
30、T THIRD-ORDER INTERCEPT 402830323436380 13 12 11 10 9 8 7 6 5 4 3 2 1INPUT COMPRESSION(dBm)FREQUENCY(GHz)0.1dB COMPRESSION POINT1dB COMPRESSION POINT12961-013 Figure 13.0.1 dB and 1 dB Compression Point vs.Frequency 402830323436380 13 12 11 10 9 8 7 6 5 4 3 2 1INPUT COMPRESSION(dBm)FREQUENCY(GHz)TA=
31、40CTA=+25CTA=+85C12961-014 Figure 14.1 dB Input Compression Point vs.Frequency over Temperature 65455055600 12 10 8 6 4 2INPUT IP3(dBm)FREQUENCY(GHz)TA=40CTA=+25CTA=+85C12961-015 Figure 15.Input Third-Order Intercept(IIP3)Point vs.Frequency over Temperature 401015202530350.01 0.1 1 10 100 1000INPUT
32、COMPRESSION(dBm)FREQUENCY(MHz)0.1dB COMPRESSION POINT1dB COMPRESSION POINT12961-016 Figure 16.0.1 dB and 1 dB Input Compression Point vs.Frequency(Low Frequency Detail)401015202530350.01 0.1 1 10 100 1000INPUT COMPRESSION(dBm)FREQUENCY(MHz)TA=40CTA=+25CTA=+85C12961-017 Figure 17.1 dB Input Compressi
33、on Point vs.Frequency over Temperature(Low Frequency Detail)65605550450.1 1 10 100 1000INPUT IP3(dBm)FREQUENCY(MHz)TA=40CTA=+25CTA=+85C12961-018 Figure 18.Input Third-Order Intercept(IIP3)Point vs.Frequency over Temperature(Low Frequency Detail)Data Sheet HMC1118 Rev.0|Page 9 of 11 THEORY OF OPERATI
34、ON The HMC1118 requires a positive supply voltage applied to the VDD pin and a negative supply voltage applied to the VSS pin.Bypassing capacitors are recommended on the supply lines to minimize RF coupling.The HMC1118 can operate with a single positive supply voltage applied to the VDD pin and the
35、negative voltage input pin(VSS)connected to ground;however,some performance degradations in the input power compression and third-order intercept can occur.The HMC1118 is controlled via two digital control voltages applied to the VCTRL pin and the LS pin.A small value bypassing capacitor is recommen
36、ded on these digital signal lines to improve the RF signal isolation.The HMC1118 is internally matched to 50 at the RF input port(RFC)and the RF output ports(RF1 and RF2);therefore,no external matching components are required.The RF1 and RF2 pins are dc-coupled,and dc blocking capacitors are require
37、d on the RF paths if the RF potential is not equal to a common-mode voltage of 0 V.The design is bidirectional;the input and outputs are interchangeable.The ideal power-up sequence is as follows:1.Power up GND.2.Power up VDD and VSS.The relative order is not important.3.Power up the digital control
38、inputs.The relative order of the logic control inputs is not important.Powering the digital control inputs before the VDD supply can inadvertently forward bias and damage the internal ESD protection structures.4.Power up the RF input.The logic select(LS)allows the user to define the control input lo
39、gic sequence for the RF path selections.With the LS pin set to logic high,the RFC to RF1 path turns on when VCTRL is logic low,and the RFC to RF2 path turns on when VCTRL is logic high.With LS set to logic low,the RFC to RF1 path turns on when VCTRL is logic high,and the RFC to RF2 path turns on whe
40、n VCTRL is logic low.Depending on the logic level applied to the LS and VCTRL pins,one RF output port(for example,RF1)is set to on mode,by which an insertion loss path provides the input to the output.The other RF output port(for example,RF2)is then set to off mode,by which the output is isolated fr
41、om the input.When the RF output port(RF1 or RF2)is in isolation mode,internally terminate it to 50,and the port absorbs the applied RF signal(see Table 7).Table 7.Switch Mode Operation Digital Control Inputs Signal Mode LS VCTRL RFC to RF1 RFC to RF2 High Low On mode.A low insertion loss path from t
42、he RFC port to the RF1 port.Off mode.The RF2 port is isolation from the RFC port and internally terminated to a 50 load to absorb the applied RF signals.High High Off mode.The RF1 port is isolation from the RFC port and internally terminated to a 50 load to absorb the applied RF signals.On mode.A lo
43、w insertion loss path from the RFC port to the RF2 port.Low Low Off mode.The RF1 port is isolation from the RFC port and internally terminated to a 50 load to absorb the applied RF signals.On mode.A low insertion loss path from the RFC port to the RF2 port.Low High On mode.A low insertion loss path
44、from the RFC port to the RF1 port.Off mode.The RF2 port is isolation from the RFC port and internally terminated to a 50 load to absorb the applied RF signals.HMC1118 Data Sheet Rev.0|Page 10 of 11 APPLICATIONS INFORMATION EVALUATION PCB Generate the evaluation PCB used in this application with prop
45、er RF circuit design techniques.Signal lines at the RF port must have 50 impedance,and the package ground leads and backside ground slug must be connected directly to the ground plane similarly to what is shown in Figure 19.The evaluation board shown in Figure 19 is available from Analog Devices,Inc
46、.upon request.12961-019 Figure 19.EV1HMC1118LP3D Evaluation PCB Table 8.Bill of Materials for the EV1HMC1118LP3D Evaluation Board1 Item Description Manufacturer2 J1 to J3 PC mount SMA RF connectors TP1 to TP5 Through-hole hold mount test points C1,C5 100 pF capacitors,0402 package U1 HMC1118 SPDT sw
47、itch Analog Devices,Inc.PCB 600-01012-00-1 evaluation PCB,Rogers 4350 circuit board material EV1HMC1118LP3D,Analog Devices,Inc.1 1 Reference this number to order the full evaluation PCB.2 The blank cells in the manufacturer column are left blank intentionally for they are user-selectable.Data Sheet
48、HMC1118 Rev.0|Page 11 of 11 OUTLINE DIMENSIONS 3.103.00 SQ2.900.300.250.201.921.70 SQ1.4810.50BSCBOTTOM VIEW TOP VIEW165 8912134EXPOSEDPADPIN 1INDICATOR*0.350.300.25SEATINGPLANE0.05 MAX0.02 NOM0.20 REF0.20 MINCOPLANARITY0.08PIN 1INDICATOR0.950.850.75FOR PROPER CONNECTION OFTHE EXPOSED PAD,REFER TOTH
49、E PIN CONFIGURATION ANDFUNCTION DESCRIPTIONSSECTION OF THIS DATA SHEET.01-08-2015-APKG-000000*COMPLIANT WITH JEDEC STANDARDS MO-220-VEED-4 WITH THE EXCEPTION OF PACKAGE EDGE TO LEAD EDGE.Figure 20.16-Lead Lead Frame Chip Scale Package LFCSP_WQ 3 mm 3 mm Body,Very Very Thin Quad(CP-16-38)Dimensions s
50、hown in millimeters ORDERING GUIDE Model1 Temperature Range MSL Rating2 Package Description Package Option Branding3 HMC1118LP3DE 40C to+85C MSL3 16-Lead Lead Frame Chip Scale Package LFCSP CP-16-38 XXXX1118 H HMC1118LP3DETR 40C to+85C MSL3 16-Lead Lead Frame Chip Scale Package LFCSP CP-16-38 XXXX11
