单个数码管verilog程序module seg1(clk,a,seg);input clk;output a;output 7:0 seg;reg 7:0 seg;reg a; reg 23:0 cnt1;reg 3:0 cnt2;always (posedge clk) begin a=1; end always (posedge clk) begin if(cnt1!=24hffffff) begin cnt1=cnt1+1; end else begin cnt1=0; cnt2=cnt2+1; if(cnt2!=10) begin case(cnt2) 4d1: seg=8b10000010; 4d2: seg=8b10111110; 4d3: seg=8b00100011; 4d4: seg=8b00011110; 4d5: seg=8b01001010; 4d6: seg=8b01000010; 4d7: seg=8b10101110; 4d8: seg=8b00000010; 4d9: seg=8b00001010; default :seg=8b11111111; endcase end else cnt2=0; end end endmodule
