1、IC Test Fundamental,Gong Xiao-Long 2013,Course Contents,Lesson 1:Overview of IC Test Lesson 2:Open/Short and DC test Lesson 3:Functional Test Lesson 4:Test Vector basic Lesson 5:ADC / DAC Lesson 6:AC testing Lesson 7:Scan / Bist / Jtag testing Lesson 8:RF testing Lesson 9:Test program Development Le
2、sson 10:Trouble Shooting,Lesson 1:Overview of IC Test,Test category The Test System PMU PE-Card,Test category,Wafer Test The testing of individual devices when they are still in wafer form. This is the first attempt at separating good dice from bad. This activity is also called wafer sort or die sor
3、t. Package Test Wafers are cut into individual dice and each die is assembled into a package. The packaged device is then tested to insure that the assembly process was correctly performed and to verify that the device still meets its design specifications. Package test is also called final test. Qu
4、ality Assurance Test Performed on a sample basis to insure that the package test was performed correctly. Device Characterization Device Characterization is the process of determining the operating extremes of individual device parameters. Pre/Post Burn-In The testing of devices before and after the
5、y are burned in to verify that the process did not cause certain parameters to drift. This process weeds out infant mortality devices (those which have a defect that causes them to fail soon after they are first used).,Military Testing Involves performing rigorous testing over a temperature range an
6、d documenting the results. Incoming Inspection Testing of devices by a customer to insure the quality of the devices purchased before using them in an application. Assembly Verification Verifies that the devices survived the assembly process and that they were assembled correctly. The tests performe
7、d during assembly verification are similar to that of package testing and may be a subset of package testing. This activity is usually performed offshore. Failure Analysis The process of analyzing device failures to determine why the device failed. Determining the cause of a failure yields informati
8、on that can improve device reliability.,Test category,The Test System,The test system is electronic and mechanical hardware used to simulate the operating conditions that a DUT will experience when used in an application, so that defective devices can be found. The test system is often known as ATE
9、or Automated Test Equipment. The test system hardware is controlled by a computer which executes a set of instructions (the test program). The tester must present the correct voltages, currents, timings and functional states to the DUT and monitor the response from the device for each test. The test
10、 system then compares the result of each test to pre-defined limits and a pass/fail decision is made. A test system is actually a collection of power supplies, meters, signal generators, pattern generators and other hardware items which all work collectively under one main controller.,The Test Syste
11、m,The CPU is the system controller. It contains the computer which controls the test system and provides a means of moving data into and out of the test system. Most new test systems offer a network interface as well as magnetic media for data transfers. The hard disk and CPU memory are used to stor
12、e information locally; the video display and keyboard are used by the test operator to interact with the test system. The DC subsystem contains the Device Power Supplies (DPS), the Reference Voltage Supplies (RVS) and the Precision Measurement Unit (PMU). The DPS supplies voltage and current to the
13、DUT power pins (VDD/VCC). The RVS supplies voltage references for logic 0 and logic 1 levels to the driver and comparator circuitry located on the pin electronic cards. These voltages set VIL, VIH, VOL and VOH. Less expensive and older test systems may have a limited number of RVS supplies, so only
14、a limited number of input and output levels can be programmed at one time. When tester pins share a resource such as the RVS, that resource is considered a shared resource. Some test systems are said to have a tester per pin architecture which means that they have the ability to set input and output
15、 levels and timing independently for each pin. A tester pin, also called tester channel, is circuitry on the pin electronics card which supplies and/or detects voltage, current and timing for one DUT pin.,The Test System,Each test system has high speed memory, called pattern memory or vector memory,
16、 to store test vectors or test patterns. Test patterns, also known as the truth table, represent the states of inputs and outputs for the various logical functions that the device is designed to perform. Input, or drive, patterns are supplied to the DUT by the test system from pattern memory. Output
17、, or expect, patterns are compared against the response from the output pins of the DUT. During a functional test, vector patterns are applied to the DUT and the DUTs responses are monitored. If the expected response data does not match the output data from the DUT, a functional failure occurs. Ther
18、e are two types of test vectors - parallel vectors and scan vectors. Many test systems support both types. The timing subsection has memory to store formatting, masking and timeset data for use during functional testing. The signal formats (wave shapes) and timing edge markers are used for DUT input
19、 signals and strobe timing for sampling DUT output signals. The timing subsection receives drive patterns from pattern memory and combines them with timing and signal format information to create formatted data which is sent to the driver section of the pin card and then to the DUT. Special Options
20、includes a variety of possibilities such as algorithmic pattern generators for memory test or specialized hardware modules used to perform analog tests. The System Clocks provide a means of synchronizing the movement of information throughout the test system. These clocks often run at much higher fr
21、equencies than the functional test rate. Many test systems have calibration circuitry which can automatically verify and calibrate the system timing.,The Test System,PMU,The Precision Measurement Unit (PMU) is used to make accurate DC measurements. It can force current and measure voltage or force v
22、oltage and measure current. Some test systems have only one central PMU that must be shared across all pin channels of the tester. Others have more than one PMU which accesses multiple channels, typically in groups of eight or sixteen. High end test systems have PMU per pin capability, which has a P
23、MU on every tester channel.,Precision Measurement Unit,Force and Measurement Modes In ATE, the term force (as in force voltage or force current) describes the application of a certain value of voltage or current by the test system. Apply can be substituted for the word force. When programming the PM
24、U, the force function is selected as either current or voltage. If current is forced, the measurement mode is automatically set to voltage. If voltage is forced, the measurement mode is automatically set to current. Once the force function is selected, the force value must be set. Force and Sense Li
25、nes To improve the voltage forcing accuracy of the PMU, a four wire system is used. Four wire systems use 2 force lines to carry current and 2 sense lines to monitor the voltage at the point of interest (usually the DUT). Ohms Law states that a voltage is produced across a resistance when current fl
26、ows through the resistance. All wire has resistance so, depending on the current through the force lines, the voltage at the DUT is different from the voltage at the PMU force unit output. Using 2 separate (non-current carrying) sense wires to measure the voltage at the DUT keeps the voltage drop ca
27、used by current flow through the force lines from causing an error or offset in the voltage. The point at which the force and sense line are connected together is called the Kelvin Connect Point.,PMU,Range Settings A PMU force range and measurement range must be selected. Proper range selection insu
28、res the most accurate test result. Be aware that the force and measure ranges have a limiting effect on the PMU. The force range will determine the maximum forcing capability of the PMU, so if the PMU is programmed to force 5 Volts and the 2 Volt force range has been selected, only 2 Volts will be f
29、orced. Likewise, if the 1mA measurement range is selected, the maximum current that can be measured is 1mA regardless of the actual current flow. It is important to note that neither the force nor the measurement range of the PMU should be changed while it is connected to a DUT. Changing the range c
30、auses noise spikes that may damage the DUT. A noise spike is when a signal level abruptly changes its voltage level for a very short time. A noise spike is also called a glitch. Limit Settings The PMU has two programmable measurement limitsan upper and a lower limit. The limits may be used individua
31、lly (one limit enabled while the other is disabled) or they may be used together (both limits enabled). The upper limit is used to make a Fail Greater Than comparison and the lower limit to make a Fail Less Than comparison. Failing the Fail Greater Than limit means the measured value was more positi
32、ve than the upper limit setting. Failing the Fail Less Than limit means the measured value was more negative than the lower-limit setting.,PMU,PMU,Clamp Settings Most Precision Measurement Units have voltage and current clamps which are set from within a test program. A clamp is a circuit that limit
33、s the amount of voltage or current that is supplied by the PMU during a test in order to protect the test operator, the test hardware and the DUT.,When the PMU is used in Force Voltage mode, a current clamp must be set to limit the maximum current which flows during the test. When forcing voltage, a
34、 PMU delivers as much current as necessary to sustain the voltage. If a DUT pin is shorted to ground (or another supply), the forcing unit will increase the current to try to force the pin to the programmed voltage. This may result in a large enough current flow through the DUT pin to burn probe car
35、ds, circuit traces, pin electronics components, fingers, adjacent DUTs, etc. When forcing voltage, the PMU measures current. Because the current clamp limits the amount of current supplied by the PMU, the current clamp value must be set outside of the test limits otherwise the current clamp will pre
36、vent a too much current failure. Previous pages Figure shows the PMU forcing 5.0V across a 250 Ohm load. In actual testing, the DUT is the resistive load. From Ohms Law (I=E/R) we know that the 250 Ohm load will restrict the current flow to 20mA during this test. The device specification may state t
37、hat the maximum acceptable current is 25mA. This means the fail limit would be set to Fail GT 25mA and the current clamp could be set to 30mA. If a defective DUT presents a load of 10 Ohms, the resulting current will be 500mA unless a current clamp is programmed to limit the current. A current flow
38、of 500mA may cause damage to the test system, the interface hardware or the DUT. However, if a current clamp is programmed to 30mA the maximum current flow would be limited by the damp circuit to a much safer value. Why 30mA? you may ask. 30mA is greater than the fail limit of 25mA, allowing the tes
39、t to fail when a defective device is encountered, but the current will be limited to a safe value. The clamp value must always be set outside of the fail limits; if not, the test will never fail.,PMU,Similar with current clamp,PMU,The pin electronics (also called the Pin Card, PE, PEC or I/O card) i
40、s the interface between the test system resources and the DUT. It supplies input signals to the DUT and receives output signals from the DUT. Each test system has its own unique design but generally the PE circuitry will contain: Driver circuitry to supply input signals. I/O switching circuitry for
41、turning drivers and current loads on and off. Voltage Comparator circuitry for detecting output levels. A connection point to the PMU. Programmable current loads. Possibly additional circuitry for making high speed current measurements. Possibly a per pin PMU Although there are many variations of th
42、is design, Figure 3-5 represents a single tester channel on a typical pin electronics card for a digital test system.,PE-Card,PE-Card,The Driver The driver circuitry receives formatted signals, called FDATA, from the high speed section of the test system. As the signal passes through the driver, the
43、 VIL/VIH references from the Reference Voltage Supplies (RVS) are applied to the formatted data. If the FDATA instructs the driver to drive to a logic 0, the driver will drive to the VIL reference. VIL (Voltage In Low) represents the maximum guaranteed voltage value that can be applied to an input a
44、nd still be recognized as a logic 0 by the DUT circuitry. If the FDATA instructs the driver to drive to a logic 1, the driver will drive to the VIH reference. VIH (Voltage In High) represents the guaranteed minimum voltage value that can be applied to an input and still be recognized as a logic 1 by
45、 the DUT circuitry. When the tester channel is programmed as an input, Fl FET turns on and the K1 relay is closed allowing the signal from the driver to pass through to the DUT. When the tester channel is programmed as an output or is in a dont care mode the Fl FET is turned off and the signal from
46、the driver will not pass through to the DUT. The Fl FET is a Field Effect Transistor used as a very high speed switch. It isolates the driver circuitry from the device under test. The Fl FET is used during IO switching, which is when the DUT alternates between receiving data from the test system (re
47、ading data) and supplying data to the test system (writing data). The same pins function as both inputs and outputs. If the tester channel is programmed as an input, the FET is on. If the tester channel is not programmed as an input the Fl FET is off, which prevents the driver signal from reaching t
48、he device under test. It is important to insure that the DUT and the driver are not trying to drive a voltage onto the same tester channel at the same time. This is called an I/O conflict ox bus contention.,PE-Card,Current Loads The Current Loads, also known as Dynamic Loads or Programmable Current
49、Loads, act as a load to the DUT outputs during functional tests and can be programmed to supply positive and negative currents. Positive current flows from the test system into the device and negative current flows from the DUT into the test system. The dynamic loads provide both IOH (Current Out High), which is the amount of current that a DUT output must source when driving a logic 1, and IOL current (Current Out Low), which is the amount of current that a DUT output must sink when driving a logic 0. After the IOL and IOH current values are set by the test program, the VREF voltage is used
