1、A /* Podem, short for path- oriented decision making;3 and Fan.4 All three algorithms operate only on combinational circuits. Our analysis focuses on the search and control mechanisms of each algorithm. We also look at the heuristics used to guide ATPG search and the notation used to represent circu
2、it values. Fujiwara5 and Bottorff give alternative views of the same algorithms. 0740-7475/88/060043$100s 1988 43 June 1988 TPG TUTORIAL GEMERATINC A TEST SET The obvious reason to test circuits is to sepa- rate good ones from faulty ones. Consider the digital circuit in Figure la, which is also rep
3、re- sented by the graph in Figure lb. The graph nodes represent circuit devices, or gates, while graph edges represent circuit interconnections, or wires. The inputs to the circuit are called pri- mary inputs. These are the only places we can apply test patterns. The outputs from the circuit are cal
4、led primary outputs. These are the only places we can observe the effects of the tests. Thus, test pattern generation is the task of find- ing a set of input patterns that will fully test the cir- cuit. These patterns, called the test set, must cause all faulty circuits to exhibit different behavior
5、 from good circuits at the primary out- puts. A failure is revealed when at least one pri- mary output is different and a failure is present. The test set must be reasonable-that is, we must be able to apply it economically to all cir- cuits produced. Testing that uses all possible input patterns wi
6、ll, of course, reveal faulty circuits but will be too expensive for large circuits with many inputs. For large circuits, the alternative to exhaustive testing is to start with some simplifying assump- tions about the possible failures. First, we assume that only stuck-at faults are failures. This ty
7、pe of fault manifests itself as a node in the cir- cuit, which permanently assumes a value of 0 or 1. If the nodes value is 0, it is called a stuck-at-0 fault; if it is a 1, it is called a stuck-at-1. Second, we assume that only one stuck-at fault is present in a faulty circuit. This single- stuck-a
8、t fault model might seem artificial on the surface, but it has been quite useful in practice. The reason is that if we can detect a large per- centage of the single stuck-at faults, we will usually get a test set that detects a correspond- ingly high percentage of all failures. We can also use stuck
9、-at fault models that have been developed for a particular technology with good tracking between predicted and actual results.* To amplify our previous definition of test pat- tern generation, then, it is the task of generating a test set that reveals all detectable single stuck- at faults. We say d
10、etectable faults because a cir- cuit can have undetectable faults, also called redundant faults. The test set must consist of binary input patterns that will reveal a difference at the primary outputs. To generate such a test set, we must produce a difference at the fault location. This process is c
11、alled fault sensitizing. We must also propagate this difference to one or more primary outputs. This process is called fault propagation. Consider the circuit in Figure 2a, which we will call a good circuit. If this circuit had a stuck-at-0 fault on the output of gate S, it would be modeled as shown
12、 in Figure 2b. FAUL T SENSITIZING To sensitize the fault, we must find a pattern that produces a value of 1 at the output of S for the good circuit. In the faulty circuit, the output of Swill be stuck-at-0 (s-a-0), which is different from the good circuit. To set S to 1 in the good circuit, we must
13、set both L and M to 1. The fault is now sensitized, since the good circuit and the faulty circuit have different values at the fault location. Figure 1. A sample combinational circuit (a) and its circuit graph (b). 44 IEEE DESIGN that is, it is undetectable, or redundant. These operations give a goo
14、d overview of what an ATPG algorithm should do. In the next M s-a-0 Primary input Figure 2. A sample good circuit (a), afaulty circuit (b), and the search graph for locating the fault (c). June 1988 45 ATPG TUTORIAL section, we will go into much more detail, but before we do, we need to stop and cla
15、rify some “sound-alike” terms that we will be using in the explanation. Pairs of words such as circuit graph and search graph and backtracing and back- tracking when used in proximity can cloud even the simplest examples. These similar sounding labels were not devised to deliberately confuse. In fac
16、t, they were not always in one discipline, but evolved separately within computer-aided design and artificial intelligence. Now these areas are merging, but it is too late to change the terms: all we can do is be aware of their differences. The circuit graph and search graph are very different, for
17、example. One is the graph of the cir- cuit, while one is the graph of the search space. Figure 2c depicts the search graph for the faulty circuit in Figure 2b. The circuit graph never changes for a given circuit and is used to build the search graph. The search graph, on the other hand, depends on b
18、oth the target fault and the search procedure. It is always a tree and is usually built by going forward from the fault site to the pri- mary outputs and going backward from inter- mediate goals to the primary inputs. Backtracing and backtracking also differ. Backtracing is used to build the search
19、graph, while backtracking is used to change a decision in the search graph. Backtracing is the process of working backward in the circuit graph to build the search graph, while backtracking is the pro- cess of correcting for some conflict between node values. K L M N Figure 3. A circuit with reconve
20、rgent fanout. THE ALGORITHMS As mentioned earlier, we have selected what we consider a representative set of ATPG algorithms for discussion here: the D algorithm, Podem, and Fan. These algorithms differ in the size of the search space, the global search strategy, and the heuristics that can be used
21、to help guide that search. The size of the search space is very important, since it determines an upper bound on the search time. The order of searching also greatly affects search time. Con- sequently, both the global search strategy used to build the search graph and the heuristics used to guide t
22、he search are just as important as the size of the search space. No matter how good the heuristic is, however, if there is a redundant fault, the search algorithm will conduct an exhaustive search before it con- cludes that the fault is indeed redundant. In this case, the size of the search space be
23、comes the dominant factor, rather than the order of the nodes in the search graph. ATPG would be quite simple for combinational circuits if it were not for something called recon- vergent fanout. A fanout point is the point at which a circuit node drives more than one other node. Node M in Figure 3
24、is an example of a fanout point, or fanout stem. Fanout stem M has two branches to gates T and S. When successor nodes of the same signal come together at a subsequent node, such as node U in Figure 3, that node is called the point of reconvergence. Each reconvergent fanout introduces dependencies i
25、n the values that can be assigned to nodes. As we will see, it is this node dependency that causes conflicts in the ATPG process. If no reconvergent fanout is pres- ent, conflicts will not occur, and we will never have to backtrack. THE D ALGORITHM The D algorithm was the first true algorithm for AT
26、PG.* We can use it to generate tests by com- bining what we know about the primitive ele- ments of the circuit with what we know about their interconnection network. The method that Roth proposed is based on the intersection of d- cubes, a notation for the difference calculus. Breuer and Friedman gi
27、ve a good background treatment of the testing aspects of the D algo- rithm in their text, while Roth offers a complete mathematical analysis in his original paper. 46 IEEE DESlGN that is, they are present from the time they first occur until the circuit is repaired or replaced. Fault coverage: The n
28、umber of faults expressed as a percentage of all faults that are detected by a set of test patterns. Fault propagation: Moving the effect of afault to a primary output by assigning values to the nodes in the search space. Fault sensitizing: Finding a set of primary input values that causes the fault
29、 site in the good circuit to have a value opposite to the faulty value (s-a-0 or s-a-1). Faulty circuit: A replicaof the original circuit with each fault site replaced by the particular fault model. The most common fault model is the single stuck-at fault. Free line: A circuit node that has no recon
30、vergent fanout nodes among its predecessors. Good circuit: The original circuit with no faults present. Headline: A free line that drives a reconvergent fanout node. Also called the root of a tree of free lines in the circuit. Implication: Determining the unique values implied by already assigned va
31、lues. This process can cause both forward and backward assignment of values. Justification: The process of finding a set of pri- mary input values that cause a node to take on the desired value; essentially the same as backtrace with conflict resolution. Primary inputs: The externally accessible inp
32、ut pins of a circuit through which we can inject logical values into the circuit. Primary outputs: The externally accessible out- put pins of the circuit through which we can observe logical values from the circuit. Reconvergent fanout: A fanout node, two or more of whose branches eventually are use
33、d as inputs to the same element. The element (one or more) at which the branches reconverge is called the point of reconvergence. Redundant fault: A fault that because of redun- dancy in the circuit cannot be detected by any static test. Also known as an undetectable fault. Sensitized path: A path t
34、hat begins at the fault site and ends at a primary output. A change in the logi- cal value of the fault site changes the logical value at the output. Single-fault assumption: The assumption that one and only one fault is present in a given circuit at a time. Stuck fault: A fault model in which the f
35、ault site has a permanent binary value (either 0 or 1). The value is assumed to be caused by the presence of afault. Test: An input pattern that will cause one or more circuit outputs to differ, depending on whether a given fault is present or absent. A test may detect more than one fault, and a set
36、 of tests is required to detect all detectable faults. All circuit nodes are initially set to X. A value of D is assigned to node T. T now has a 1 in the good circuit and a 0 in the faulty circuit. The next step is to justify this assignment. That is, we must make sure that the assignment results in
37、 no con- flicts. Since the faulty circuit is assumed to be stuck at 0, the assignment must first of all cause the good circuit to have a 1 at T. Both inputs of T must be 1, so M and R are assigned a 1. Since M is a primary input, its value is already justified. To justify R to 1, K and L must also b
38、e 1. Once again, since these nodes are inputs, they are immedi- ately justified. Thus, R is justified, and T is justi- fied. At this point, the fault is sensitized with justified values and the goal becomes fault propagation. If the D value is to propagate from T to a pri- mary output, it must pass
39、through AND gate U. For this to be successful, all the other inputs to IEEE DESIGN & TEST Of COMPUTERS 48 the gate must be set to 1. The result is that S is assigned a value of 1. Since M is already assigned 1, the only way to produce the 1 on S is to set N to 0. Because N is a primary input, the 0
40、at N is immediately justified. We have propagated the D to the output of U. We must now propagate it to Z. Fortunately, since Z is directly connected to U, we do not need to set any more nodes. We can observe the D at primary output Z, so we have found a test. The algorithm records the test, along w
41、ith the expected good circuit output of 1 at Z and the target fault for which the test was generated. BACKTRACKING The example just given is somewhat straight- forward in that we found no conflicts. If we had encountered a conflict, we would have needed to backtrack, node by node, in the search spac
42、e. Backtracking, as we said earlier, con- sists of reexamining each nodes assignment starting backwards from the location of the con- flict. The algorithm checks to see if untried alter- native assignments will remove the conflict. Backtracking continues until the conflict disap- pears or until the
43、entire search space has been exhausted. If the space is exhausted, then the fault is redundant and no test exists. To illustrate this process, we return to the fault propagation example (Figure 3). Suppose we try to propagate the D at T through U before justifying the inputs to T. Figure 4b shows th
44、is case. We begin by setting S to 1. If we justify this assignment by setting M to 0, then when we try to justify the D value at T, we will encounter a con- flict. The already assigned value of 0 at M will conflict with the 1 value required to justify T=D. To resolve this conflict, we would have to
45、backtrack through the entire tree we used to sensitize the fault as well as the one we used to propagate it until we reach node M. At that time, we could choose N as an alternative way to set S to 1, as depicted by the dashed line in Figure 4b, and the search would proceed. ANALYSIS The D algorithm
46、is relatively blind to global cir- cuit details. In our example, sensitizing the fault before propagating it worked best. For many cir- cuits, however, it is better to propagate before sensitizing. We will always need to backtrack for some circuit with some target fault unless the cir- cuit graph is
47、 a tree. Because very few circuits June 1988 Figure 4. AD algorithm search graph without a con- flict (a) and with a conflict (b). 49 ATPG TUTORIAL .- “.U,.- All nodes are set to X except M r have this tree-like property, we must provide for backtracking. In addition, because of node dependencies in
48、 the search graph, the D algorithm contains hid- den conflicts that often cause it to continue beyond the conflict point before the conflict is detected. The example we looked at had only one path for propagating D from the fault site to a primary output. Many circuits have more than one such path.
49、If more than one path exists, then the algorithm must try each path individually as well as all possible combinations of two paths, three paths, etc., up to the total number possible. Implications R=l, T=D S=l, U=D, Z=D Implications T=O, S=l I 1 1 R=l, T=D I S=l, U=D Z=D Figure 5. A Podem search graph without backtrack- ing (a) and with backtracking (b). The result is an explosion of algorithmic com- plexity. Armstrong, lo among others, has tried to reduce this complexity by using a single-path approach to fault propagation. This approach, called single-path sensitization, restricts th
