1、 HX8347-A 240RGB x 320 dot, 262K color, with internal GRAM, TFT Mobile Single Chip Driver Version 01 September, 2007 ( DOC No. HX8347-A-AN )-P.1- Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or
2、 in part without prior written permission of Himax. September, 20071. Introduction.4 2. HX8347-A Chip Block Diagram5 3. HX8347-A PAD Assignment.6 3.1 Alignment mark . 7 3.2 Bump size . 8 4. Pin Description9 5. HX8347-A Reference FPC circuit (For CMO 3.2” / 2.4” / 2.8”LCD Panel) 13 5.1 Command-parame
3、ter interface mode. 13 5.1.1 MPU Interface . 13 5.1.2 RGB interface 14 5.2 Register-content interface mode. 15 5.2.1 MPU interface 15 5.2.2 RGB with Serial interface 16 6. LCD POWER GENERATION.18 6.1 LCD Power Generation Scheme 18 6.2 Various Boosting Steps . 19 7. Software Configuration 20 7.1 Feat
4、ures 20 7.1.1 Display. 20 7.1.2 Display module 20 7.1.3 Display/Control interface . 20 7.1.4 Others 21 7.2 GRAM mapping 22 7.3 Scan Function . 23 7.4 Interface Mode 24 7.4.1 Interface Mode Selection 24 7.4.2 Register-Content Interface Mode 24 7.4.3 Serial Data Transfer interface . 33 7.4.4 Command-P
5、arameter Interface Mode. 35 7.4.5 RGB Interface 41 7.5 Initial Procedure 44 7.5.1 Power Supply Setting Flow . 44 7.5.2 Display on/off Setting Flow 45 7.5.3 Standby Mode Setting Flow 46 7.6 Initial code for reference . 47 7.6.1 The reference setting of Normal Display for Command-Parameter Interface M
6、ode 47 7.6.2 The reference setting of Normal Display for Register-Content Interface Mode 48 7.6.2.1 The reference setting of CMO 3.2” Panel 48 7.6.2.2 The reference setting of CMO 2.4” Panel 50 7.6.2.3 The reference setting of CMO 2.8” Panel 52 7.6.3 The reference setting of into Standby mode for Re
7、gister-Content Interface Mode. 54 7.6.4 The reference setting of exit Standby mode for Register-Content Interface Mode. 55 8. Revision History56 HX8347-A 240RGB x 320 dot, 262K color, with internal GRAM, TFT Mobile Single Chip Driver List of Contents September, 2007-P.2- Himax Confidential This info
8、rmation contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007Figure 2. 1 HX8347-A block diagram 5 Figure 5. 1 Reference FPC circuit Command-parameter interface modes MP
9、U interface 13 Figure 5. 2 Reference FPC circuit of Command-parameter interface modes Serial + RGB interface. 14 Figure 5. 3 Reference FPC circuit of Register-content interface modes MPU interface 15 Figure 6. 1 LCD power generation scheme 18 Figure 6. 2 Various boosting steps 19 Figure 7. 1 Memory
10、Map. (240RGBx320). 22 Figure 7. 2 MY, MX, MV Setting 23 Figure 7. 3 Input Data Bus and GRAM Data Mapping in 8-Bit Bus System Interface with 18( 6 + 6 + 6 ) Bit-Data Input (“BS2, BS1, BS0”=”011”) 25 Figure 7. 4 Input Data Bus and GRAM Data Mapping in 16-Bit Bus System Interface with 16 Bit-Data Input
11、 (“BS2, BS1, BS0”=”000”). 25 Figure 7. 5 Input Data Bus and GRAM Data Mapping in 16-Bit Bus System Interface with 18(16+2) Bit-Data Input (“BS2, BS1, BS0”=”001”) . 25 Figure 7. 6 Input Data Bus and GRAM Data Mapping in 16-Bit Bus System Interface with 18(6+6+6) Bit-Data Input (“BS2, BS1, BS0”=”100”)
12、 . 26 Figure 7. 7 Input Data Bus and GRAM Data Mapping in 18-Bit Bus System Interface (“BS2, BS1, BS0”=”010” or ”101”). 26 Figure 7. 8 Register read/write Timing in Parallel Bus System Interface (for I80 series MPU) 27 Figure 7. 9 GRAM read/write Timing in 16-/18-bit Parallel Bus System Interface (f
13、or I80 series MPU). 28 Figure 7. 10 GRAM read/write Timing in 8-bit Parallel Bus System Interface (for I80 series MPU). 29 Figure 7. 11 Register read/write Timing in Parallel Bus System Interface (for M68 series MPU). 30 Figure 7. 12 GRAM read/write Timing in 16-/18-bit Parallel Bus System Interface
14、 (for M68 series MPU). 31 Figure 7. 13 GRAM read/write Timing in 8-bit Parallel Bus System Interface (for M68 series MPU). 32 Figure 7. 14 Data Write Timing in Serial Bus System Interface 33 Figure 7. 15 Data Read Timing in Serial Bus System Interface 34 Figure 7. 16 GRAM Write Data Mapping for 16 b
15、it interface 36 Figure 7. 17 GRAM Write Data Mapping for 8 bit interface 36 Figure 7. 18 Register Read/Write Timing in Parallel Bus System Interface (for I80 series MPU) 37 Figure 7. 19 Register read/write Timing in Parallel Bus System Interface (for M68 series MPU) 38 Figure 7. 20 GRAM Read/Write T
16、iming in Parallel Bus System Interface (for I80 series MPU). 39 Figure 7. 21 GRAM Read/Write Timing in Parallel Bus System Interface (for M68 series MPU). 40 Figure 7. 22 RGB Interface Circuit Input Timing . 41 Figure 7. 23 18 bit / pixel Data Input of RGB Interface . 42 Figure 7. 24 16 bit / pixel
17、Data Input of RGB Interface . 43 Figure 7. 25 Power Supply Setting Flow. 44 Figure 7. 26 Display On/Off Setting Flow 45 Figure 7. 27 Standby Mode Setting Flow 46 HX8347-A 240RGB x 320 dot, 262K color, with internal GRAM, TFT Mobile Single Chip Driver List of Figures September, 2007-P.3- Himax Confid
18、ential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007Table 5. 1 Connected Capacitor 17 Table 5. 2 Connected Schottkey diode 17 Table 7. 1 MY, MX
19、, MV Setting . 23 Table 7. 2 Interface Mode Selection 24 Table 7. 3 MPU selection in Register-content Interface Circuit. 24 Table 7. 4 Interface Selection in Register-content Interface Mode . 24 Table 7. 5 Data Pin Function for I80 Series CPU 24 Table 7. 6 Data Pin Function for M68 Series CPU 24 Tab
20、le 7. 7 The Function of RS and R/W Bit bus . 33 Table 7. 8 MPU selection in Command-Parameter Interface Circuit. 35 Table 7. 9 Interface Selection in Command-Parameter Interface Mode . 35 Table 7. 10 Data Pin Function for I80 Series CPU 35 Table 7. 11 Data Pin Function for M68 Series CPU 35 Table 7.
21、 12 EPL bit Setting and Valid ENABLE Signal 41 September, 2007HX8347-A 240RGB x 320 dot, 262K color, with internal GRAM, TFT Mobile Single Chip Driver List of Tables-P.4- Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced,
22、 or disclosed in whole or in part without prior written permission of Himax. September, 20071. Introduction This document describes Himaxs HX8347-A 240RGBx320 dots resolution driving controller. The HX8347-A is designed to provide a single-chip solution that combines a gate driver, a source driver,
23、power supply circuit for 262,144 colors to drive a TFT panel with 240RGBx320 dots at maximum. The HX8347-A can be operated in low-voltage (1.65V) condition for the interface and integrated internal boosters that produce the liquid crystal voltage, breeder resistance and the voltage follower circuit
24、for liquid crystal driver. In addition, The HX8347-A also supports various functions to reduce the power consumption of a LCD system via software control. The HX8347-A is suitable for any small portable battery-driven and long-term driving products, such as small PDAs, digital cellular phones and bi
25、-directional pagers. The HX8347-A supports three interface modes: Command-Parameter interface mode, Register-Content interface mode and RGB interface mode. Command-Parameter interface mode and Register-Content interface mode are selected by the external pins IFSEL0 setting, and RGB interface mode is
26、 selected by internal bit RGB_EN. September, 2007HX8347-A 240RGB x 320 dot, 262K color, with internal GRAM, TFT Mobile Single Chip Driver Version 01 -P.5- HX8347-A 240RGB x 320 dot, 262K-Color TFT Controller Driver APPLICATION NOTE V01Himax Confidential This information contained herein is the exclu
27、sive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 20072. HX8347-A Chip Block Diagram NCS MPU IF Serial IFRGB IF18-bit16-bitGateDriverGrayscale voltage generatorVTESTVMONIGamma adjusting circuitSourc
28、edriverD/A ConvertercircuitData LatchC11A/C11BS1 S720Internal registerOTPGRAM controlGRAMTimingControlStep Up1Mode selectionStep Up2 Step Up3CX11A/CX11BDDVDHC21A/C21BC22A/C22BVGHVGLC12A/C12BVCLVCOM CricuitVCOMHVCOMLVCOMRVCOMTVCOMHITVMAGNRD_ENWR_RNWDNC_SCLV063G1G320VGH/VGLP68,EXTCBS20, IFSEL0NISD, BU
29、RNNRESETENABLEVSYNCHSYNC3TEST31TS8098VSSDVSSAGenerator TimingRCOSCOSCVCIPowerRegulatorVBGPVDDD18D170DOTCLK18-bit16-bit8-bitSDISDORGB IFMPU IF Serial IFFigure 2. 1 HX8347-A block diagram -P.6- HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver APPLICATION NOTE V01Himax Confidential
30、This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 20073. HX8347-A PAD Assignment Figure 3. 1 HX8347-A pad assignment -P.7- HX8347-A 240RGB x 320 dot, 26
31、2K color, TFT Mobile Single Chip Driver APPLICATION NOTE V01Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 20073.1 Alignment mark
32、A_MARK (A1) A_MARK (A2) -P.8- HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver APPLICATION NOTE V01Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior writ
33、ten permission of Himax. September, 20073.2 Bump size Input PAD Output PAD -P.9- HX8347-A 240RGB x 320 dot, 262K color, TFT Mobile Single Chip Driver APPLICATION NOTE V01Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced,
34、or disclosed in whole or in part without prior written permission of Himax. September, 20074. Pin Description Input Parts Signals I/O Pin Number Connected with Description Select the MPU interface mode as listed below Use with IFSEL0=1 Register-content interface mode P68 BS2 BS1 BS0 Interface mode D
35、B pins 000016-bit bus interface, 80-system, 65K-Color D17-D16: Unused, D15-D0: Data 000116-bit bus interface, 80-system, 262K-color D17-D16: Unused, D15-D0: Data 001018-bit bus interface, 80-system, 262K-color D17-D0: Data 00118-bit bus interface, 80-system, 262-Color D17-D8: Unused D7-D0: Data 0100
36、16-bit bus interface, 80-system, 262-Color D17-D16: Unused, D15-D0: Data 010118-bit bus interface, 80-system, 262K-color D17-D0: Data 100016-bit bus interface, 68-system, 65K-Color D17-D16: Unused, D15-D0: Data 100116-bit bus interface, 68-system, 262K-color D17-D16: Unused, D15-D0: Data 101018-bit
37、bus interface, 68-system, 262K-Color D17-D0: Data 10118-bit bus interface, 68-system, 262K-color D17-D8:Unused D7-D0: Data 110016-bit bus interface, 68-system, 262K-Color D17-D16: Unused, D15-D0: Data 110118-bit bus interface, 68-system, 262K-color D17-D0: Data X 1 1 ID Serial bus IF DNC_SCL, SDO,SD
38、I Use with IFSEL0=0 Command-Parameter interface mode P68 BS2 BS1 BS0 Interface mode DB pins 001 X 16-bit bus interface, 80-system, D17-D16:Unused, D15-D0: Data 000 X 8-bit bus interface, 80-system, D17-D8:Unused, D7-D0: Data 101 X 16-bit bus interface, 68-system, D17-D16:Unused, D15-D0: Data 100 X 8
39、-bit bus interface, 68-system, D17-D8:Unused, D7-D0: Data x 1 1 x Serial interface D17-D0:Unused SDI, SDO P68, BS2,BS1,BS0 I 4 VSSD/ IOVCC (Other setting is inhibited) IFSEL0 I 1 MPU Interface format select pin IFSEL0 Interface Format Selection 0 Command-Parameter interface mode 1 Register-content i
40、nterface mode In this case, the IFSEL0 has to be connected to IOVCC. EXTC I 1 MPU Extended command set enable. (Only support Command-Parameter Interface mode IFSEL0=0) Low: extended command set is discarded High: extended command set is accepted If operate in Register-content interface mode, the EXT
41、C can be connected to IOVCC or VSSD. NCS I 1 MPU Chip select signal. Low: chip can be accessed; High: chip cannot be accessed. Must be connected to VSSD if not in use. NWR_RNW I 1 MPU I80 system: Serves as a write signal and writes data at the rising edge. M68 system: 0: Write, 1: Read. Fix it to IO
42、VCC or VSSD level when using serial buss interface. NRD_E I 1 MPU I80 system: Serves as a read signal and read data at the low level.M68 system: 0: Read/Write disable, 1: Read/Write enable. Fix it to IOVCC or VSSD level when using serial buss interface. -P.10- HX8347-A 240RGB x 320 dot, 262K color,
43、TFT Mobile Single Chip Driver APPLICATION NOTE V01Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. September, 2007Input Parts Signals I/O Pin N
44、umber Connected with Description BURN I 1 MPU Free Running mode If BURN=Hi, this can enable free running mode for burn in test. The display data alternates between full black and full white independent of input data in free running mode. SDI I 1 MPU Serial data input pin. If not used, please let it
45、connected to IOVCC or VSSD. DNC_SCL I 1 MPU The signal for command or parameter select under parallel mode(i.e. Not serial interface): Low: command. High: parameter. When under serial interface, it servers as SCL. VSYNC I 1 MPU Frame synchronizing signal. Has to be fixed to IOVCC level if is not use
46、d. HSYNC I 1 MPU Frame synchronizing signal. Has to be fixed to IOVCC level if is not used. ENABLE I 1 MPU A data ENABLE signal in RGB I/F mode. Has to be fixed to VSSD level if unused (High active, if EPL=0). DOTCLK I 1 MPU Dot clock signal. Has to be fixed to VSSD level if is not used. NRESET I 1
47、MPU or reset circuit Reset pin. Setting either pin low initializes the LSI. Must be reset after power is supplied. OSC I 1 Oscillation Resistor Oscillator input for test purpose. If not used, please let it open or connected to VSSD. VCOMR I 1 Resistor or open A VcomH reference voltage. When adjustin
48、g VcomH externally, setregisters to halt the VcomH internal adjusting circuit and place a variable resistor between VREG1 and VSSD. Otherwise, leave this pin open and adjust VcomH by setting the internal register of the HX8347-A. VGS I 1 VSSD or external resistor Connect to a variable resistor to ad
49、justing internal gamma reference voltage for matching the characteristic of different panel used. Output Part Signals I/O Pin Number Connected with Description S1S720 O 720 LCD Output voltages applied to the liquid crystal. G1G320 O 320 LCD Gate driver output pins. These pins output VGH, VGL.(If not used, should be open) VCOM O 1 TFT common electrode The power supply of common voltage in TFT driving. The voltage amplitude between VCOMH and VCOML is output. Connect this pin to the common electrode in TFT panel. TE O 1 MPU Tearing effect output. If not used, please open this p
