1、IC Design Engineer Test SheetAnalog DesignDevice Knowledge1. p+/n- junction and p-/n+ junction, which has a higher breakdown voltage? Why? For a p+/n- junction having NA and ND, what is the approximate function of junction capacitance (Cj) vs. reverse biased voltage (VR)?2. Draw the cross-section of
2、 a CMOS inverter. Draw the parasitic structure on the cross-section. Describe ways to prevent “latch-up”?Circuit Analysis3. See the figure below.a. Draw the bode plot for this circuit.b. Estimate the systematic offset in this amplifier.c. Which is the positive input?VC CRO 2I+-VI NO U TCRO 1W / LM04
3、. See the figure below.a. What is this circuit?b. Which input is the positive input?c. How much current flows in P2?d. If I=10uA, what is a good selection for the value of R?e. What is the Common Mode Input Range for this circuit?f. What is the Common Mode Output Range for this circuit?g. Assume the
4、 only capacitance is from OUT to GND. Draw a Bode Plot.h. Assume no load. What is the maximum positive slew rate if COUT=C? What is the maximum negative slew rate?VC CIIP2P3N0N1N2P1P0G N DR R R1 0 / 1 1 0 / 1 1 0 / 1M = 2O U T5. See the figure below.Assume at time=0 inductor current is 0A. Draw indu
5、ctor current, VX and VOUT vs. time.1 IL1 u HVXVO U TI1 A1 u S 2 u S tI6. See the figure below.a. What is this circuit?b. What is the desired ratio R2/R1?c. How many stable points does this circuit have?d. Assume R1 and R2 have no Temperature Coefficient. Draw a graph of I in R2 vs. Temperature.e. Wh
6、at is the minimum supply voltage necessary for this circuit to work properly?P0P1VO U TVC C1 0 / 1 1 0 / 18 : 1Q0Q1R1R27. See the figure below.a. Write the gain equation of each circuit.b. Assuming VO=0 at time 0. Sketch VO(t) for the given input signal.+-RRA+-CRB+-RCRCtVi n8. Draw Buck Converter Ci
7、rcuit and key waveform, explain the basic operations at steady state.OtherMust Answer (Question 1-3)Question 1:Write the V/I relationship equations for resistor (R), capacitor (C), and inductor (L).Question 2:Given VB in Table 1, please calculate VC and VE. Assumptions: beta of NPN is infinity, P-N
8、junction forward voltage drop is 0.7V.Q1VCR21 0 K+ 4 0 VR21 0 KVCVBB e t a = I n f i n i t y , P - N j u n c t i o n f o r w a r d d r o p i s 0 . 7 VVB VE VC0V10.7V20.7VQuestion 3:假设图中理想放大器工作在深度负反馈状态，请计算下图输出端电压（V OUT） 。+-3 K O h m5 K O h m5 VFor Test Engineer (Question 4-5)Question 4：用 C 语言写一个递归算法求
9、 N!Question 5：C 语言题目a. 在 VC6.0 编译环境下，下列类型变量需要占几个字节内存：intfloatdoublelongcharunsigned charb. 以下程序的输出结果：#define ADD(x) (x)+(x)main()int a=4, b=6, c=7, d=ADD(a+b)*c;printf(“d=%dn”,d);c. 设 int a=7,b=9,t;执行完表达式 t=(ab)?a:b;后，t 的值是？d. 设计一个排序函数，并同时获得最大值，最小值，均方根。函数名、排序数列等自行定义。For AE Engineer (Question 6-8)Que
10、stion 6:a. What is this circuit shown in the Figure?D1V1R3C1V2b. Please draw the waveforms for V2 for three cases (use the same scale):C1=open, R3=1k;R3=open, C1=1uF;R3=1k, C1=1uF.tV1- 2 V1 0 V0 V2 m stV20 VQuestion 7:Draw bode plots of VO/VI (gain and phase) for the circuit shown below. Please labe
11、l the proper pole/zero location.-+R 1 = 1 KR3VIR2C11 K 1 u FVO+ 1 0 V- 1 0 VCase 1: R3=openCase 2: R3=1KQuestion 8:Figure below shows a simple buck converter. The switching frequency of the converter is 1MHz.VGVI N= 1 0 VQ2VS WL11 u HVO U TC21 0 0 u FD2IO U Ta. VIN=10V, VOUT=4V, IOUT=5A, what is the
12、 ON time of Q2?b. Draw waveforms of VSW and IL1 below (under the same time scale of VG-VSW).Assumption: IOUT=5A.For Layout Engineer (Question 9-12)Question 9:简述 CMOS 工艺流程。Question 10：Draw the layout of a two-input NAND gate.M1M2VD DM3M4ZABQuestion 11：下面电路图中有两个 MOSFET(MA and MB)。假设每个 MOSFET 有两个 gate figure，右下版图应该如何连接，才能使 MA 和 MB 匹配。MAMBVD DGDADBGQuestion 12：画出不同的电流镜图，并简述各自特点。
