1、 Video Decoder and Display Processor Preliminary Technical Data ADV7186Pr. 0.5| Page 1 of 32 FEATURES 3D comb video decoder Overlay support for external graphical HMI/OSD Fastboot and bitmap load from external EEPROM LVDS transmitter 1and receiver (OpenLDI) Hardware downscaling/upscaling to QVGA and
2、 WXGA panel resolutions Fully differential analog input LCD controller Qualified for automotive applications Video Decoder NTSC/PAL/SECAM color standards support NTSC/PAL 2D/3D motion detecting comb filter Advanced time-base correction (TBC) with frame synchronization Vertical peaking and horizontal
3、 peaking filters Robust synchronization extraction for poor video sources Any-to-any, 3 3 color space conversion (CSC) matrix Video Signal Processor Edge adaptive interlaced-to-progressive conversion of 525i and 625i Overlay support for external graphical HMI/OSD Bitmap overlay from EEPROM/serial/pa
4、rallel interface Low cost Bitmap OSD requiring no external memory Hardware downscaling/upscaling to QVGA and WXGA panel resolutions Adaptive contrast enhancement (ACE) Up-dither of course resolution input signals Flip/mirror orientation control Analog Input Single low power 10-bit analog-to-digital
5、converter (ADC) 6-channel analog input mux Single-ended or fully differential input Three channel anti-aliasing filter 525i-/525p-/625i-/625p-/720p-/1080i- component analog input RGB graphics up to 800 600 at 60 Hz (SVGA) Digital Input Flexible 24-bit pixel input interface LVDS receiver (OpenLDI) 1S
6、erial or parallel DMA interface Digital Output Flexible 24-bit pixel output interface LVDS transmitter (OpenLDI) 1Independent BT656 output channel LCD Controller Timing controller (TCON) for LCD panels 2PWM backlight control Programmable gamma correction General Dual standard identification (STDI) f
7、unction support One programmable interrupt request output pin Spread spectrum output pixel clock Support for low-power mobile DDR (MDDR) and DDR2 SDRAMAPPLICATIONS Navigation radios and Infotainment head units Central console and rear seat monitors Parking guide and ADAS vision systems Pico and mini
8、 projectors Industrial monitors and displays FUNCTIONAL BLOCK DIAGRAM Figure 1. ADV7186 Functional Block Diagram Figure 2. ADV7186-T Functional Block Diagram1Not available on ADV7186-T 2ADV7186-T only ADV7186 Preliminary Technical DataPr. 0.5| Page 2 of 32 TABLE OF CONTENTS Features 1 A pplications
9、. 1 Functional Block Diagram 1 Revision History . 2 General Description . 3 Detailed Functional Block Diagram 4 S pecif ica t io ns . 5 Electrical Characteristics . 5 Analog Specifications . 7 Video Specifications . 8 Timing Characteristics 9 Data and I 2 C Timing Characteristics . 9 Timing Diagrams
10、 10 Absolute Maximum Ratings 11 Package Thermal Performance . 11 ESD Caution 11 Pin Configuration and Function Descriptions ADV7186 12 Pin Configuration and Function Descriptions ADV7186-T 18 Functional Overview 24 Analog Front End . 24 Digital Inputs 24 Digital Output . 24 LCD Controller . 24 Stand
11、ard Definition Processor . 24 Component Processor . 25 Video Signal Processor 25 Other Features 26 External Memory Requirements 27 Low Power Mobile Double Data Rate . 27 Double Data Rate 2 27 Digital Input/Output Formatting . 28 LVDS Receiver Features 28 LVDS Transmitter Features 128 Pixel Data Inpu
12、t Modes Features . 28 Host Interface Input Features . 28 Pixel Data Output Modes Features 28 BT656 Output Channel . 28 LCD Controller . 28 Overlay Function 29 Low Cost on-chip Bitmap OSD 29 Register Map Architecture 30 Outline Dimensions . 31 Ordering Guide 31 REVISION HISTORY 02/06/11 Revision Pr.
13、0.5 Added information on up-dither and Low Cost OSD features 17/04/11 Revision Pr. 0.4 Changed pinout of BT656 buses Added detail regarding backlight control signals 03/29/11 Revision Pr. 0.3 Added BT656 channel 03/16/11 Revision Pr. 0.2 Updated with new pinout (DVDDIO) 1/01/11 Revision Pr. 0.1 Adde
14、d ADV7180-T description Updates throughout document 1/10/10Revision Pr. 0: Initial Version Preliminary Technical Data ADV7186Pr. 0.5 | Page 3 of 32 GENERAL DESCRIPTION The ADV7186 is a high performance, single chip, multiformat video decoder and processor with integrated LVDS Tx 1and LVDS Rx 1 . The
15、 ADV7186 analog front end comprises a single high speed, 10-bit ADC that digitizes the analog video signal. The ADV7186 analog front end supports input resolutions up to SVGA (800 600 at 60 Hz). The ADV7186 has 48 pixel pins, of which 24 are input and 24 are output. The ADV7186-T contains identical
16、features to the ADV7186 apart from having a TCON output in place of the LVDS Tx output and no LVDS Rx. The multiformat decoder contains a standard definition processor (SDP) supporting the conversion of PAL, NTSC, and SECAM standards in the form of a composite or an S-Video input signal into a digit
17、al ITU-R BT.656 format. The ADV7186 contains one main component processor (CP), which processes YPbPr and RGB component formats, including RGB graphics. The ADV7186 analog front end supports the decoding of these RGB/YPbPr video signals into a digital YCbCr or RGB pixel output stream. The support fo
18、r component video includes 525i, 525p, 625i, 625p, 720p and 1080i standards while VGA to SVGA graphic rates are supported. The CP core can also process video from the input pixel pins or LVDS Rx 1 . The video signal processor can perform edge-adaptive intra-field de-interlacing, ensuring excellent p
19、erformance on low angle edges as well as antiflickering filtering. The video signal processor allows scaling between common video resolutions enabling up to WXGA output (the output frame rate is always equal to the input field/frame rate). ACE offers improved visual detail. Flip/mirror capability al
20、lows for compensation of the different camera mounting orientations. An independent BT656 channel allows access to the output of the SD and CP cores. Simultaneously, the output pixel bus or 1Not available on ADV7186-T 2ADV7186-T LVDS TX 1can drive out video data which has been received via the input
21、 pixel bus or the LVDS RX 1bus. In the case of the ADV7186, the pins used for the BT656 channel are shared with the external memory interface. In the case of the ADV7186-T the pins used for the BT656 channel are shared with both the external memory interface and the TCON pins, leaving it to the user
22、 to select the prefered option. The ADV7186 can accept up to two layers of overlay on the main picture. The sources of this overlay can be TTL/LVDS Rx 1and/or EEPROM bitmap, parallel/serial host interface. These layers can be overlaid on the input video stream using alpha blending and chroma keying.
23、 Additional to the full overlay functionality described above, the ADV7186 also supports a bitmap OSD function which requires no external memory. This feature allows overlay on a pre-defined section of the display using a one foreground and one background color, allowing for a warning or information
24、 banner to be displayed over the viewed video. The LCD controller function includes TCON 2signals enabling ADV7186-T to drive glass-only panels. PWM backlight control enables a programmable dimming ratio. In order to compensate for nonlinearity in the video system, the ADV7186 allows a 32-point gamm
25、a correction curve to be applied independently on each output channel (RGB or Y cbCr). Where boot time is critical, the ADV7186 has a hardware configurable Fastboot feature enabling video to be displayed directly after power-up. Bitmaps stored in the EEPOM can also be loaded and displayed on power-u
26、p. The ADV7186W models are automotive qualified. The ADV7186 is fabricated in an advanced CMOS process. It is provided in a 12 mm 12 mm, 196-ball, CSP BGA, surface- mount, RoHS-compliant package and is specified over the -40C to +85C temperature range. ADV7186 Preliminary Technical DataPr. 0.5| Page
27、 4 of 32 DETAILED FUNCTIONAL BLOCK DIAGRAM Figure 3. Detailed Functional Block Diagram for ADV7186 and ADV7186-T Preliminary Technical Data ADV7186Pr. 0.5 | Page 5 of 32 SPECIFICATIONS AVDD = 1.8 V 5%, DVDD = 1.8 V 5%, PVDD = 1.8 V 5%, DVDDIO = 1.8V to 3.3 V 5% 1, SAVDD = 1.8 V 5%, SDVDD = 1.8 V 5%,
28、 LRVDD = 1.8 V 5%, LTVDD = 1.8 V 5%, TMIN to TMAX = -40C to +85C, unless otherwise noted. ELECTRICAL CHARACTERISTICS Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit STATIC PERFORMANCE Resolution (each ADC) N 10 Bits Integral Nonlinearity INL 27 MHz (at a 10-bit level) TBD LSB 54
29、MHz (at a 10-bit level) TBD LSB 74.25 MHz (at a 10-bit level) TBD LSB 108 MHz (at a 10-bit level) TBD LSB 170 MHz (at a 9-bit level) TBD LSB Differential Nonlinearity DNL 27 MHz (at a 10-bit level) TBD LSB 54 MHz (at a 10-bit level) TBD LSB 75 MHz (at a 10-bit level) TBD LSB 108 MHz (at a 10-bit lev
30、el) TBD LSB 170 MHz (at a 9-bit level) TBD LSB DIGITAL INPUTS Input High Voltage VIH 2 V Input Low Voltage VIL 0.8 V Input Current IIN RESET pin 120 A Other digital inputs 10 A Input Capacitance CIN 10 pF DIGITAL INPUTS (5 V Tolerant) 1Input High Voltage VIH 2.6 V Input Low Voltage VIL 0.8 V Input C
31、urrent IIN 82 +82 A OPEN LDI INPUTS Single Ended. Input Voltage Range 825 1575 mV Differential Threshold Voltage 100 mV Differential Input Impedance 100 OPEN LDI OUTPUTS Differential Output Voltage 247 350 454 mV Offset Output Voltage 1.125 1.2 1.375 V Output Short Circuit Current 12 mA DIGITAL OUTP
32、UTS Output High Voltage VOH 2.4 V Output Low Voltage VOL 0.4 V High Impedance Leakage Current ILEAK 10 A Output Capacitance COUT 20 pF POWER REQUIREMENTS Digital Core Power Supply DVDD 1.71 1.8 1.89 V Digital I/O Power Supply DVDDIO 3.14 3.3 3.46 V PLL Power Supply PVDD 1.71 1.8 1.89 V Analog Power
33、Supply AVDD 1.71 1.8 1.89 V LVDS Tx Supply LTVDD 1.71 1.8 1.89 V LVDS Rx Supply LRVDD 1.71 1.8 1.89 V 11.8V DVDDIO supported up to 54MHz only ADV7186 Preliminary Technical DataPr. 0.5| Page 6 of 32 Parameter Symbol Test Conditions/Comments Min Typ Max Unit Memory Interface Digital Power Supply SDVDD
34、 1.71 1.8 1.89 V Memory Interface Analog Power Supply SAVDD 1.71 1.8 1.89 V Digital Core Supply Current IDVDD TBD mA Digital I/O Supply Current IDVDDIO TBD mA PLL Supply Current IPVDD TBD mA Analog Supply Current I AVDD TBD mA LVDS Tx Supply Current I LT V D D TBD mA LVDS Rx Supply Current ILRVDD TB
35、D mA Memory Interface Digital Power Supply ISDVDD TBD mA Memory Interface Analog Power Supply ISAVDD TBD mA Power-Down Currents I DVDD TBD mA I DVDDIO TBD mA I PVDD TBD mA I AVDD TBD mA I LT V D D TBD mA I LRVDD TBD mA I SDVDD TBD mA I SAVDD TBD mA Power-Up Time tPWRUP TBD ms 1The following pins are
36、 5 V tolerant: HS_AIN and VS_AIN. Preliminary Technical Data ADV7186Pr. 0.5 | Page 7 of 32 ANALOG SPECIFICATIONS Table 2. Parameter Test Conditions/Comments Min Typ Max Unit CLAMP CIRCUITRY 1Input Impedance Clamps switched off 10 M Analog (AIN1 AIN6) ADC Midscale (CML) 0.91 V ADC Full Scale Level CM
37、L + 0.55 V ADC Zero Scale Level CML 0.55 V ADC Dynamic Range 1.1 V Clamp Level (when locked) Component input, Y signal CML 0.12 V Component input, Pr signal CML V Component input, Pb signal CML V PC RGB input (R, G, B signals) CML 0.12 V CVBS input CML 0.205 V CVBS differential input CML 0.205 V S-V
38、ideo input (Y signal) CML 0.205 V S-Video input (C signal) CML V Large Clamp Source Current SDP only 0.3 mA Large Clamp Sink Current SDP only 0.4 mA Fine Clamp Source Current SDP only 9 A Fine Clamp Sink Current SDP only 8 A 1Specified for external clamp capacitor of 100 nF. ADV7186 Preliminary Tech
39、nical DataPr. 0.5| Page 8 of 32 VIDEO SPECIFICATIONS Table 3. Parameter Symbol Test Conditions/Comments Min Typ Max Unit NONLINEAR SPECIFICATIONS Differential Phase DP CVBS input (modulated five-step) TBD Degrees Differential Gain DG CVBS input (modulated five-step) TBD % Luma Nonlinearity LNL CVBS
40、input (modulated five-step) TBD % NOISE SPECIFICATIONS Measured at 27 MHz LLC SNR Unweighted Luma ramp TBD dB SNR Unweighted Luma flat field TBD dB Analog Front-End Crosstalk TBD dB LOCK TIME SPECIFICATIONS (SDP) Horizontal Lock Range 5 % Vertical Lock Range 40 70 Hz Subcarrier Lock Range fSC 0.8 kH
41、z Color Lock-In Time 60 Lines Sync Depth Range 120 200 % Color Burst Range 1 200 % Vertical Lock Time 300 ms Horizontal Lock Time 100 Lines CHROMA SPECIFICATIONS (SDP) Chroma Amplitude Error 0.4 % Chroma Phase Error 0.3 Degrees Chroma Luma Intermodulation 0.2 % 1Nominal sync depth is 300 mV at 100%
42、sync depth range. Preliminary Technical Data ADV7186Pr. 0.5 | Page 9 of 32 TIMING CHARACTERISTICS Data and I 2 C Timing Characteristics Table 4. Parameter 1Symbol Test Conditions/Comments Min Typ Max Unit CLOCK AND CRYSTAL Crystal Frequency, XTAL 28.63636 MHz Crystal Frequency Stability 50 ppm Horiz
43、ontal Sync Input Frequency 10 110 kHz LLC Frequency Range 6 86 MHz I 2 C PORTS SCL Frequency 400 kHz SCL Minimum Pulse Width High t1 600 ns SCL Minimum Pulse Width Low t2 1.3 s Start Condition Hold Time t3 600 ns Start Condition Setup Time t4 600 ns SDA Setup Time t5 100 ns SCL and SDA Rise Time t6
44、300 ns SCL and SDA Fall Time t7 300 ns Stop Condition Setup Time t8 0.6 s RESET FEATURE Reset Pulse Width 5 ms CLOCK OUTPUTS LLC Mark-Space Ratio t9:t10 45:55 55:45 % duty cycle DATA AND CONTROL OUTPUTS 2Data Output Transition Time SDR (CP) t 11 End of valid data to negative clock edge TBD ns Data O
45、utput Transition Time SDR (CP) t 12 Negative clock edge to start of valid data TBD ns Data Output Transition Time SDR (SDP) t 13 End of valid data to negative clock edge TBD ns Data Output Transition Time SDR (SDP) t 14 Negative clock edge to start of valid data TBD ns DATA AND CONTROL INPUTS 3Input
46、 Setup Time (Digital Input Port) t 15 HS_DIN, VS_DIN TBD ns DE_DIN, Data inputs TBD ns Input Hold Time (Digital Input Port) t 16 HS_DIN, VS_DIN TBD ns DE_DIN, Data inputs TBD ns 1Guaranteed by characterization. 2Timing figures obtained using default strength value. 3TTL input values are 0 V to 3 V,
47、with rise/fall times 3ns, measured between the 10% and 90% points. ADV7186 Preliminary Technical DataPr. 0.5| Page 10 of 32 TIMING DIAGRAMS Figure 4. I 2 C Timing Figure 5. Pixel Port and Control SDR Output Timing (CP) Figure 6. Pixel Port and Control SDR Output Timing (SDP) Figure 7. Digital Input
48、Port and Control Input Timing 07748-003 SDA SCL t 5 t 3 t 4 t 8 t 6 t 7 t 2 t 1 t 3 08850-004 t 9 LLC P0 TO P35, HS/CS, VS/FIELD, DE t 11 t 12 t 10 08850-005 t 9 LLC P0 TO P35, VS, HS, DE/FIELD t 13 t 14 t 10 t 18 t 17 CLKIN CONTROL INPUTS P30 TO P39, P40 TO P43, P44 TO P53 HS_IN1, VS_IN1, HS_IN2, V
49、S_IN2, DE_IN 06760-007Preliminary Technical Data ADV7186Pr. 0.5 | Page 11 of 32 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating AVDD to GND 2.2 V DVDD to GND 2.2 V PVDD to GND 2.2 V DVDDIO to GND 4.0 V LRVDD to GND 2.2 V LTVDD to GND 2.2 V SDVDD to GND 2.2 V SAVDD to GND 2.2 V AVDD to PVDD 0.3 V to +0.3 V AVDD to DVDD 0.3 V to +0.3 V PVDD to DVDD 0.3 V to +0.3 V LRVDD to DVDD 0.3 V to +0.3 V LRVDD to PVDD 0.3 V to +0.3 V LTVDD to DVDD 0.3 V to +0.3 V SDVDD to SAVDD 0.3 V to +0.3 V Digital I
