1、Allegro 中常用之 Properties (V 14.1) Property 可加入之对象 可否在线路图中加入 ALT_SYMBOLS Device yes AUTO_GENERATED_TERM Component no AUTO_RENAME Reference Designator (Component) no BOARD_THICKNESS Board no BOM_IGNORE Component yes BUS_NAME Net y CLIP_DRAW Design (board), Symbol no CLIP_DRAWING Connect line, Device, P
2、in, Filled rectangle, Line, Rectangle, Shape, Symbol, Via, Void no CLOCK_NET Net yes COMPONENT_WEIGHT Reference Designator (Component) yes C_TEMPERATURE Reference Designator (Component) yes DENSE_COMPONENT Reference Designator (Component) yes DFA_DEV_CLASS Board, Symbol no DIFFERENTIAL_PAIR Net yes
3、DIFFP_2ND_LENGTH no DIFFP_LENGTH_TOL Net no DRIVER_TERM_VAL no ECL N yes ECL_TEMP et EDGE_SENS Net, Xnet, ECSet no ELECTRICAL_CONSTRAINT_SET Net yes FILLET Connect Line no FIRST_INCIDENT Net, Xnet, ECSet no FIX_ALL Reference Designator (Component) yes FIXED Reference Designator (Component), Symbol,
4、Connect Line, Filled rectangle, Line, Net, Pin, Rectangle, Shape, Via yes FIXED_T_TOLERANCE TPoint no FP_BOARD_CLEARANCE Board no FP_NOTES_TEXT_BLOCK Board no FP_REFDES_TEXT_BLOCK Board no FP_ROOM_NAME_TEXT_BLOCK Board no GROUP Function Designator yes HARD_LOCATION Reference Designator, Function Des
5、ignator yes, but not seen in schematic as LOCATION HEAT_SINK_FACTOR Reference Designator (Component) yes IDF_OWNER All Objects no IMPEDANCE_RULE Net, ECSet no INSERTION_CODE Device yes J_TEMPERATURE Reference Designator (Component) yes LEAD_DIAMETER Board, Symbol no LOAD_TERM_VAL Net no LOGICAL_PATH
6、 Function Designator (Component) yes, but assigned by PXL. Not user defined. MAX_BOND_LENGTH Net, Connect Line no MAX_BVIA_STAGGER Net no MAX_EXPOSED_LENGTH Net, ECSet yes MAX_FINAL_SETTLE yes MAX_OVERSHOOT Net, ECSet yes MAX_PARALLEL (PARALLELISM) Net, Connect Line, ECSet no MAX_PEAK_XTALK (MAX_PEA
7、K_CROSSTALK) Net no MAX_POWER_DISS Device, Reference Designator (Component) yes MAX_SSN Net no MAX_STUB_LENGTH yes MAX_UNDERSHOOT Net, Connect Line yes MAX_VIA_COUNT Net, ECSet yes MAX_XTALK (MAX_CROSSTALK) Net no MAX_XTALK (MAX_CROSSTALK) Net, Connect Line no MIN_BVIA_GAP Net no MIN_BVIA_STAGGER N
8、no MIN_FIRST_SWITCH et,ECSet no MIN_HOLD Net, Pin yes MIN_LINE_WIDTH Net, Connect Line yes MIN_NECK_WIDTH Net, Connect Line yes MIN_NOISE_MARGIN Net, ECSet yes MIN_SETUP NPin yes NET_PHYSICAL_TYPE Net, Constraint Area (Shape, Rectangle) yes NET_SCHEDULE Net, ECS no NET_SPACING_TYPE Net, Constraint A
9、rea (Shape, Rectangle) yes NO_DRC Pin, Va no NO_GLOSS Net yes NO_LIN2SHAPE_FAT Connect Line no NO_PIN_ESCAPE Reference Designator (Component) , Net, Pin yes NO_RAT Net yes NO_RIPUP NO_ROUTE Reference Designator (Component), Net yes NO_SHAPE_CONNECT Pin, Va yes NO_SWAP_GATE Reference Designator, Func
10、tion Designator yes, but assigned by PXL. See PXL documentation. NO_SWAP_GATE_EXT Function Designator yes, but assigned by PXL. See PXL documentation. NO_SWAP_PIN Reference Designator, yes, but assigned by PXL. See Function Designator, Pin PXL documentation. NO_TEST Net yes NO_VIA_CONNECT Pins, Vias
11、 no PACKAGE_HEIGHT_MAX and PACKAGE_HEIGHT_MIN Rectangle, Shape no PARALLELISM (MAX_PARALLEL) Connect Line, Net no PIN_ESCAPE Reference Designator, Pin yes PIN_SIGNAL_MODEL Pin no PINUSE P yes, but assigned by PXL. See PXL documentation. PLACE_TAG Reference Designator (Component) no PLATING Shape no
12、PROBE_NUMBER Net yes PROPAGATION_DELAY Nt, ECSet no PULSE_PARAM Net, Xnet, Bus, Diff Pair no RATED_CURRENT Device yes RATED_MAX_TEMP Device yes RATED_POWER Device yes RATED_VOLTAGE Device yes RATSNEST_ SCHEDULE Net, ECSet no REF_DES_FOR_ASSIGN Function no RELATIVE_PROPAGATION_DELAY Net, ECSet no REU
13、SE_ID Compnent, Symbol REUSE_INSTANCE Component yes REUSE_MODULE Component yes REUSE_NAME Component yes REUSE_PID Component, Symbol ROOM Reference Designator, Function Designator yes ROOM_TYPE Room Boundary no ROUTE_PRIORITY Net yes ROUTE_TO_SHAPE no SAME_NET Nets no SHIELD_NET yes SHIELD_TYPE Net S
14、LOTNAME Function no STUB_LENGTH Net,ECS yes SWAP_GROUP Function Designator yes, but assigned by PXL. not user-assigned. SYS_CONFIG_NAME Board no T_TEMPERATURE Reference Designator (Component) yes TERMINATOR_PACK Device no TESTER_GUARDBAND Net,Pin no THERMAL_RELIEF Thermal Connect Line no THICKNESS L
15、ayout Cross Section no TIMING_DELAY_OVERRIDE Net, Pin no TOL Device yes TOPOLOGY TEMPLATE Net yes TOPOLOGY_TEMPLATE_REVISION Net, ECSet yes TOTAL_ETCH_LENGTH Xnet, net, bus or diff pair yes TS_ALLOWED Net yes UNFIXED_PINS Board, Symbol no VALUE Discrete Device yes VIA_LIST Net no VOLTAGE Reference D
16、esignator (Component) yes WEIGHT Pin no WIRE_LENGTH Net yes XTALK_ACTIVE_TIME N, ECSet no XTALK_IGNORE_ NETS et no XTALK_SENSITIVE_TIME Net, ECSet no ALIGNED Attached to bondpads in APD. Prohibits the attached bondpad from going out of alignment when the MOVE or SPIN commands are invoked. The proper
17、ty is set by the tool, depending upon configurations invoked in the Options tab. ALT_SYMBOLS 外型变换宣告 加在 device 上 (through a device file). 列出会用到的各种外型名称 . 其语法为 PACKAGEPROP ALT_SYMBOLS (Subclass:Symbol,.;Subclass:Symbol,.) Subclass-Either TOP (or T) for top layer, or BOTTOM (or B) for bottom layer Symbo
18、l-Standard Allegro/APD package symbol name 例如 74LS373 其正面也可换成 SOIC20 背面可换成 SOIC20,SOIC20_PE PACKAGEPROP ALT_SYMBOLS (TOP:SOIC20;BOTTOM:SOIC20,SOIC20_PE) AUTO_GENERATED_TERM SPECCTRAQuest internally generated property. Not accessible to the user. AUTO_RENAME 下次可自动更名 加到 reference designator (component
19、). 宣告此零件在下次零件自动更名时可被执行 . Value is TRUE. BOARD_THICKNESS Generated automatically by Allegro/APD and attached to a board (design). Specifies board (or layout) thickness. Allegro/APD computes the thickness by adding all layer thicknesses in the cross section. Cadence recommends that you do not assign t
20、he BOARD_THICKNESS property. BOM_IGNORE 零件不列 BOM 中 A reserved property for parts in a design. BOM_IGNORE specifies a string value attached to a component instance. Any component instance that has this property with a non-blank value is not displayed in the Bill of Materials report. BOND_PAD Generate
21、d automatically by APD and attached to bond pads created during the automatic or interactive wire bond process. BUS_NAME 定总线名称 Attach to a net. Name of net to be treated as a bus by interactive and automatic routing. Concept adds this property automatically for signals identified as part of a bus. Y
22、ou can also attach this property interactively. Value is a string. C_TEMPERATURE Generated and attached to a reference designator (component). Defines the case temperature for the component in degrees centigrade. CLIP_DRAW 图块贴入序号 Generated automatically by Allegro/APD and attached to the design, in
23、the format CLIP_n, where n is the total number of times, plus one, that the paste operation was used in the layout or symbol drawing. You can use the CLIP_n value to track the number of times clipboard information has been pasted into a drawing. CLIP_DRAW always stores one more than the current numb
24、er of operations. You can change the CLIP_n value to another number by editing the property interactively (using the Process - Edi t - Property option). CLIP_DRAWING 被贴入图块序号 Generated automatically by Allegro/APD in the format CLIP_n, where n is the number of times that an element in a clipboard fil
25、e was pasted into a layout or symbol drawing. Allegro/APD attaches this property to all elements (connect lines, pins, filled rectangles, lines, rectangles, shapes, symbols, vias, and voids) except text, in a clipboard file whenever you paste the clipboard file into a layout or symbol drawing. For e
26、xample, if the property CLIP_DRAWING = CLIP_3 is attached to a pin, it means that the pin in a clipboard file has been pasted into a particular design or symbol drawing as part of the third paste operation. CLK_2OUT_MAX The maximum delay from the active clock range at a latch to the output change. C
27、LK_2OUT_MIN The minimum delay from the active clock range at a latch to the output change. CLK_SKEW_MAX Used by the Timing Setup/Hold tab of the constraint manager. Defines the maximum skew in the clock signal between the launching and latching components. This property defines a value in nanosecond
28、s and can be attached to either the data net or a pin in the data net. CLK_SKEW_MIN Used by the Timing Setup/Hold tab of the constraint manager. Defines the minimum skew in the clock signal between the launching and latching components. This property defines a value in nanoseconds and can be attache
29、d to either the data net or a pin in the data net. CLOCK_NET The CLOCK_NET property is related to the SpecctraQuest timing spreadsheet and the File - Import - Timing command. The Import Timing command adds this property on a net to store the name of the net that is used to clock the nets data. For e
30、xample, if there is a net DATA1, that is clocked by net CLOCK1, then DATA1 would get the CLOCK_NET property added with the a value of CLOCK1. COMPONENT_WEIGHT 自动摆设零件之权数 Attach to a reference designator (component). Used by automatic placement to determine the relative importance of components. Value
31、 is an integer from 0 to 100. All components have a default weight of 50. CURRENT Attach to a reference designator (component). Defines the current consumed by the component in amperes. Used by Thermax and Viable. DENSE_COMPONENT 联机数多之零件 ,自动布线程序会较先走线 Attach to a reference designator. Indicates the c
32、omponent is heavily connected to other components. Ratsnesting attempts to put the pins on these components at the end of their net schedule. Also, the automatic router routes connections to a dense component first. Value is TRUE. DFA_DEV_CLASS Used to classify devices as per the DFA required classi
33、fication. As of now, the only legal value is AL. It labels a component as Axial. DIFFERENTIAL_PAIR 差动讯号线对名 ,须将两线对设同一名称 Attach to a net. The name of the differential pair. To create a differential pair, assign two nets with a DIFFERENTIAL_PAIR property that have the same name. Used by automatic routi
34、ng and constraint checking. DIFFP_2ND_LENGTH 同差动讯号线对可允许之最大间距 Attach to a net. The secondary differential pair maximum line-to-line length. This is the maximum length a pair of nets can run at a distance apart specified by the Secondary Differential Pair Maximum line-to-line separation. Used by autom
35、atic routing and DRC checking. DIFFP_LENGTH_TOL 同差动讯号线对可允许之最大线长差距 Attach to a net. The allowable difference between the total lengths of two differential pair nets. The value is either an absolute distance or a percentage of total net length. Used by automatic routing and DRC checking. DRIVER_TERM_V
36、AL 驱动端之终端电阻值 Attach to a net. The value of a terminator component to be added to the driver end of the net. Used by the automatic terminator assignment program. ECL 高速讯号宣告 ,可配合 Tool/Report/ECL.列出线长 ,贯孔树等报表 Attach to a net. Identifies a high speed net. Value is either TRUE or FALSE. Used by automatic
37、 routing and ratsnest scheduling. If the ECL property is attached to a net, Allegro/APD assumes a stub length of zero and a ratsnest schedule of SOURCE_LOAD_DAISY_CHAIN. You can override this property by assigning the STUB_LENGTH property or the RATSNEST_ SCHEDULE property. ECL_TEMP Attached to nets
38、 to be processed by the terminator assignment program in incremental mode. EDGE_SENS This constraint property defines whether or not a receiver pin is sensitive to non-monotonicity in the waveform. The value of this constraint shows which edges of the waveform are sensitive, that is, rising edge onl
39、y, falling edge only, both edges, or neither edge. ELECTRICAL_CONSTRAINT_SET 电气宣告组名 Attach to a net. The name of the Electrical Constraint Set to apply to the net. Any net that does not have an ELECTRICAL_CONSTRAINT_SET property has the default ECSet. EMC_COMP_TYPE String that specifies a variable t
40、hat identifies the component type. Used by EMControl. EMC_CRITICAL_IC String that identifies the class of a critical IC. Used by EMControl. EMC_CRITICAL_NET String that identifies the class of a critical net. Used by EMControls. EMC_RUN_DIR When you save changes to the EMC Initialization form, the E
41、MC run directory name is stored in a design-level property called EMC_RUN_DIR. Used by EMControl. FAILURE_RATE Generated by Viable and attached to a reference designator (component). The components rate in failures in units that correspond to the calculation method (usually failures per million hour
42、s) used by Viable. FILLET 泪滴处理 Attach to connect lines. Indicates the connect lines are for filleting around a pad or line join. Prevents DRC from identifying dangling connect lines Value is TRUE. This property is assigned by the pad fillet glossing function. FIRST_INCIDENT This constraint property
43、defines whether a signal is required to switch on the first incident wave. The value of this constraint shows which edges of the waveform must switch on thie first incident wave. The legal values are rising edge only, falling edge only, both edges or neither edge. FIX_ALL 锁逻辑关系使不可 SWAP Attach to a r
44、eference designator (component). Indicates that no swapping can be performed on this component, its functions, or its pins. FIXED 锁对象使不可更动 ,如移动删除更改等等 . Attach to components, symbols, nets, pins, vias, clines, lines, filled rectangles, rectangles, and shapes. Indicates that the object cannot be moved
45、 or deleted,the automatic router is not to rip up connections in the net, and that glossing is not to be performed on the net. Value is TRUE. FIXED_T_TOLERANCE 分歧点之布线可移动范围 Attach to a Tpoint. Specifies a radius around a Tpoint that the router can route to the Tpoint. FP_BOARD_CLEARANCE SPECCTRAQuest
46、 internally generated property. Not accessible to user. FP_NOTES_TEXT_BLOCK SPECCTRAQuest internally generated property. Not accessible to user. FP_REFDES_TEXT_BLOCK SPECCTRAQuest internally generated property. Not accessible to user. FP_ROOM_NAME_TEXT_BLOCK SPECCTRAQuest internally generated proper
47、ty. Not accessible to user. GROUP 将逻辑闸宣告为同一零件 Attach to a function designator (gate). The name of the group to which the component belongs. Allegro/APD assigns functions that have the same GROUP property value to the same component. The grouping of components lets you control the assignment of funct
48、ions to components. HARD_LOCATION 固定零件名称 ,使不被更名 Attach to a reference designator (component) or a function designator (gate). Prevents the reference designator of a component from being automatically or interactively renamed. Value is TRUE. HEAT_SINK_FACTOR Attach to a reference designator (componen
49、t). A number used as a multiplier to represent increased surface area. Used by Thermax. IDF_OWNER IDF 3.0 allows entities to be owned be Electrical tool (like Allegro) or a mechanical tool. It may be edited by the user to change the ownership. Legal values are ECAD and MCAD. IMPEDANCE_RULE Attach to a net. Specifies an impedance restriction between any two pins on a net or between any pin and Tpoint connection on a net. Used by DRC checking and routing. If a connection has an impedance constraint specified by both an IMPEDANCE_RULE property and an electrical cons
