1、null)null nullM ICROPROCESSORSnullv? “ !9a/nullFPGA !9 H5ZE*林昌辉,樊晓桠(西北工业大学航空微电子中心,西安 710065)null nullKnull1:对数字电路而言,提高工作频率至关重要,因为更高的工作频率意味着更加强大的处理能力b以可编程逻辑设计基本原则之一的null面积与速度的平衡与互换原则null为指导思想,介绍了几种 FPGA设计中通过消耗逻辑资源提高工作频率的设计思想和技巧b1oM:现场可编程逻辑;面积和速度;时序约束;逻辑复制ms |: TP303null nullDS M : Anull nullcI|: 1002
2、- 2279(2007)03- 0006- 04The Principle andMethods of ImprovingW orking Tmi ing in FPGA DesignLIN Chang- hu,i FAN Xiao- ya(Avia tion M icroelectron ics Cen ter, Northw estern Polytechnical University, X inull an 710072, China)null null Abstract: To the digital circui,t enhancing the design frequency i
3、s very importan,t because thehigher frequency means more powerful processing ability. Basing on the null balance and interchangebetween area and speednull principle, introducing several design skills of improving working tim ing byconsum ingmore logical resource in FPGA design.Key words: FPGA; Area
4、and Speed; Tim ing Constraints; Logic duplicated1nullnullASIC(“ ) q !91va 85a la ?av 3 H+,$v 0 5b.dASIC !9i“ 7?ag v,+Y BQg f /1 f bFPGA ASICg -1 m , FPGA a ? VI q 2I+, V ASIC !9 _,YVFPGA9 V 5 /ASIC 7? ,V7g Bbt b0 !932RISC) null C-nullR2 ,) “ , =i5 , i,9L g,Load/Store ?q, !9X , ? r400 ,T q233MH zb- F
5、PGAV, P7?A ltera stratix DSP S80, PFPGA A lteraStratix“ q, q|EP1S80B956C6, LE( ) 79040, )6,BGAb PQuartus II ! f / nQ8 L,!9 V L “S q, h 56% (44262LE), |Lz !9/FPGA k H) T q40MPb9L H66M, r5 = T “S,1 !9 , P) T q 666MbVI !9 =? p V,7 B null 5null, !9 lFPGA4 H, V I nYV B“ m4 !9 H,9 null nullbv FPGA“d !9 =
6、4 !9,7 O9null nullB4T HZE4 b2null 5 null null B !9 hFPGAnull3 2007 M6nullnull No. 3Jun. , 2007null* “:SE1 S “( 60573143);v 370( Z200646)nullTe: ( 1982- ), 3,Z 2 , V 3,Z_:9 8“ASIC“d !9bnull l : 2006- 06- 14: FPGA !9 H5ZE bFPGA ,9 (? (FF)sV(LUT)b !9 N !9 hFPGA 9 Bn Z Tbnull null !9T H ?rK q, q !9 H %b
7、 !9 HaPAD to PAD Timeay HWa HW H H H+_ MM1b S:,“FPGA !9 S, !9 NSb B dB 8b1 pB !9 H !9 Kl, qK, C Lb S !9 “S !9 H1 p(c !9K q1 p) -4/,Kl , ? /, P !9H v, qb “S s8C Xb1 1 p,e “d !9 = 4 !9 p,7 M M1b T !9 H 1 v, q1 ,5i“ !9r ,“d ; 6BZ , !9 h l, LC ? v,1 ,“d9 vdhbT Fs, B“bM1/, HaT q1 p1Bt, l H,B 55b FPGA !9B
8、1 XbV ,B !9 T H v, ? q !91 p, * ?YV ? v h !9h , ;Q, TB !9 H1 p, YZEr !9 q, * B VYV| 1i,i T v, i) , v) nulli1nullbV4 A, ) 1 p,M | 4b3null !9 X/ F3. 1null BKYV9F HHq m bZEK | bB|1 z)H,9 ) H, V ?C m1Pm UBt HbN H %ZEYV| h H, m Ubm1nullYV hl HRISC) !9i“ f b r v !9, 7s 1 r ,_r ? 7VC f ,B - 7|1 zr bN - 7|
9、,Nh | br v 8, -8 f 1 V1 UbV1null -8T1 HW P ( LE )8 (MH z) -825 387. 1869 422. 12null null1 TA UYV , !9 9F , T q B4 6b 9 ) |1$,| v H ?$ H1| b3. 2null1i1i X 6B8CbL !FPGA ) v) Kv100Mbits/s, T q 300Mbits/s,5 A) vs ? 1 pb f/, null null X, ) v, m2 U, n5| 1i, 3 vi) s ,K|) Tnulli1null, q1pb) v A, q 300Mbits
10、/s,7FPGA = A, 0 v) q 100Mbits/s, !9 , LC ) b9 ,|1i,BYV ,4 !9s , YV h4“dT qbnull7nullnull 3 null)null nullm2null1i 3. 3null: Z : Z l /:F( a, b, c) = aF(1, b, c) + ( a) F(0, b, c)Vl V A,: Z L= 5 v e Q_ , L= MYV 4 qb: Z YV9F4 ,V7 5)a F | H,V7h 1o Hb1 !9B v19 B Vr T:lzc_eq= ( ( ( ( l_en) | op_a) + op_b)
11、 = = a_bus) A|l_en 1o |, HKvb PAmplify3. 6 v8,iQuartusII LC, P 27LE,Ktpd HW13nsb/ |Vr T: Z , !9:assign lzc_eq_0= ( ( ( 1+ op_a) + op_b) = = a_bus)assign lzc_eq_1= ( l_en) ( ( op_a+ op_b) = a_bus)assign lzc_eq= ( l_en)? lzc_eq_0: lzc_eq_1;MBl_en4|,lzc_eq_0lzc_eq_1 |214 byN, l_en|5)$4b PAmplify3. 68,i
12、QuartusIIB “S q LC, P35LE,Ktpd HW12. 4nsb| H , !9 9FN,null nullB8Cb4null PEDA 4T H| !9 )VV,g 4 8 Lb tEDA , V !9,5 “ 5 5Z_bEDA !9T H1 YV !9F“ H , H V?S !9 H,Vr !9 HHqbYVF V e 8a a L,hl L H,V74T qb FPGA L A lteraStratix“ q,yN L AlteraQuartusII 4. 0b4. 1null Quartus II HQuartus II ! GQF / H :( 1)Megafu
13、nction PM egafunction A lteraaqK vVC, !9 PM egafunction , ?| VN I ,1 Mega-function8 LCT1I ?b !9 PRAM, FIFO, PLL( H s ), PMegafunction LC,v !9T Hb+Y1 , PQuartusII 3 V,T 5, ,9 ?v4 !9 ?b( 2) 5 !Assignments/Settings 4Analysisnull8null 2007 Mnull null: FPGA !9 H5ZEtDELAY qWF ; tw ire L; tSU 7i % Hy HW; t
14、CLK_SKEW H |bfmax ?88C !9 H ?, K1 HSBbQuartus II K Hs , !fmaxY H ?NHK H , t Vs !91o b( 4) I/O H !“Assignments/Settings 4Tim ing Requirements?. / M .: S, 2001. 4 null J Candy. A Use ofDouble Integration in Sigma DeltaM od-ulation J. IEEE T rans. Commum, Vo.l 33, pp. 249-258, M ar. 1985. 5 null V Pelu
15、so, M Steyaert, and W Sansen. Design of Low -voltage Low- powerCMOS Delta- sigma A /D convertersM . K luwerAcadem icPublishers, ISBN0- 7923- 8417- 2, 1999. 6 null Letizia Lo Prest.i EfficientM odified- Sinc F ilters for Sig-ma , 2003. 3 null1. Verilog 3“d !9M .:t?t bv, 2003. 4 nullb . ASICFPGA J.9 , 2004,30( 8): 10- 12. 5 nullp,1.FPGA /CPLD LCEDA !9 J.+, 2004, 23( 2): 6- 8 6 null 3,m. FPGAASIC !9 J.0/ , 2001, 29( 6): 50- 52.null13nullnull 3
