1、1 FPGA时序优化方法 课程安排 时序收敛流程 如何解决 FPGA中存在的时序问题 通过 FPGA设计工具进行时序优化 实例 2 课程安排 时序收敛流程 如何解决 FPGA中存在的时序问题 通过 FPGA设计工具进行时序优化 实例 3 4 设计完成后，如何判断一个成功的设计？ 设计是否满足 面积要求 -是否能在选定的器件中实现；通常资源占用率不要超过 85%。 设计是否满足 性能要求 -能否达到要求的工作频率。 管脚定义 是否满足要求 -信号名、位置、电平标准及数据 流方向等。 成功的 FPGA设计 5 如何判断设计适合所选芯片？ 所选芯片是否有足够的资源容纳更多的逻辑？如果有，有多少？ M
2、emory资源有多少 BITS? 如果适合所选芯片 , 能否完全成功布通 ? 手段：查看 Map Report 或者 Place if(e =d) end 2012/9/20 16 充分利用 IP资源 17 编码注意事项 Use pipeline stages more bandwidth Use synchronous reset better system control Use inferable resources Multiplexer Shift Register LUT (SRL) Block RAM, LUT RAM Cascade DSP Avoid high-level c
3、onstructs (loops, for example) in code Many synthesis tool produce slow implementations 18 面向综合的 RTL开发 敏感信号表应尽可能完整 。当敏感信号表不完整时，综合前后的网表仿真可能会不对应。在组合逻辑块中，敏感信号表一定要包含这个过程或块读入的每个信号。对于时序块，敏感信号表一定要包含时钟和其他控制信号。另外，也要避免敏感信号表中出现不必要的信号，因为它们会降低仿真速度。 在 Verilog中，对于 时钟块应使用非阻塞赋值 ，否则， RTL级和门级的行为会不同。 RTL代码应该以一定的方式划分，使综
4、合过程更有效，时序要求更容易实现。例如，编写一个状态机，代码可以分为两个过程 组合逻辑和时序逻辑。 相关的 组合逻辑应该在同一模块 中；不同综合目标的模块应该分开；将相关逻辑功能分在一组也能避免块之间的时序依赖关系。 应该 避免在顶层设计中调用门级逻辑 。顶层逻辑阻止工具优化带有块逻辑的门级逻辑。如果在 SOC中使用了多个相同的核。胶联逻辑应该放在核内部。例如，时钟域缓冲器和总线接口门可以放在核内，使胶联逻辑变成简单的互连线。 19 Synthesis guidelines Use timing constraints Define tight but realistic individual
5、 clock constraints Put unrelated clocks into different clock groups Use proper options and attributes Turn off resource sharing Move flip-flops from IOBs closer to logic Turn on FSM optimization Use the retiming option 20 约束的影响 21 Place & Route Guidelines Timing constraints Use tight, realistic cons
6、traints Recommended options High-effort Place & Route By default, effort is set to Standard Timing-driven MAP Tools to help meet timing Floorplanning(Use the PACE and PlanAhead software tools) Physical synthesis tools Other available options: Incremental design 22 工具中 Constraints的影响 了解 FPGA特性，正确设定目标
7、 每种型号的 FPGA都有性能极限，工艺不同，性能也不同 峰值频率（仅 1 logic level） Spartan-6 (400 MHz) Virtex-6 (650 MHz) Virtex-5 (550 MHz) 以上频率是非常理想的情况，布线延迟很短 那么典型值是多少呢 ? 要求良好的 timing estimate 23 性能预估 Performance estimates are available before implementation is complete Synthesis Report Logic delays are accurate Routing delays a
8、re estimated based on fanout Reported performance is generally accurate to within 30 percent Post-Map Static Timing Report Logic delays are accurate Routing delays are estimated based on placement and fanout 性能预估 Synthesis tools have access to logic delays, but not net delays To resolve this, synthe
9、sis tools use a loading model as a net delay estimate Up to 50% uncertainty Xilinx still recommends that you review your synthesis tools timing estimate Experienced FPGA designers know that another estimate is to use the 50/50 rule This assumes that your logic delay (Tilo + Tsu + Tckdi delay) will t
10、ypically equal an average net delay From the Virtex-6 data sheet (using the -3 speed grade, fastest device) Tilo = .18ns, Tsu = .29ns, and Tckdi = .30ns Tlogic = .77ns and Troute .77ns for an estimate of 1.54ns for 1 logic level (this corresponds to the 650 MHz estimate) Likewise, 2 logic level 3.08
11、ns and 3 logic level 4.62ns 25 性能预估 请记住 A logic level is a clock-to-out on a CLB可配置逻辑块 register, plus a LUT delay, plus a setup time on a CLB register Tckdi + Tilo + Tsu Your performance is greatly impacted by the number of logic levels FPGA experts know if you want to improve your system speed, fir
12、st make sure you have evaluated the number of logic levels on your timing critical path 26 Performance Estimates 经验缺乏的工程师 typically design their worst case path at 3 to 5 logic levels Worst case path 7.7ns = 129 MHz 具有经验的工程师 typically design their worst case path at 2 logic levels Worst case path 4.
13、62 = 324 MHz But this will depend on the effort you put in to follow good HDL coding techniques and optimize your design for your FPGA architecture Replicating logic to reduce high fanout net delays Pipeline to reduce logic levels Using alternative design techniques to reduce logic levels Using your
14、 synthesis options to reduce logic levels Using advanced implementation options to improve the place and route solution 27 28 静态时序分析 Post-map： Map后，使用 Post-map timing report确定关键路径的逻辑延迟 Post-PAR： PAR后，使用 Post-PAR static timing report确定时序约束是否满足 Logic delay Vs. Routing delay： 60%/40%原则 Timing Analyzer可
15、以读取时序报告，查找关键路径，并与 Floorplanner协同解决时序问题 使用 Timing Analyzer 查看时序报告 29 Timing Analyzer GUI Hierarchical browser Quickly navigate to specific report sections Failing constraints indicated with a red “X” Timing objects window Summarizes the path displayed in the path detail window Report text Logic highlighted in blue can be cross-probed
