1、CHAPTER 1 OVERVIEW,1 Concept of DSP1) DSP(Digital Signal Processing) the Algorithms Reserching 2) DSP(Digital Signal Processor) the Device to realize the algorithms,This users guide discuss the TMS320C5x generation of fixed _point digital signal processors(Dsps) in the TMS320 family. The C5x DSP pro
2、vides improved performance over earlier C1x and C2x generations while maintaining upward compatibility of source code between the devices.,2 TMS320C Family Overview,The TMS320C family consisits of two types of single-chip DSPs: 16-bit fixed-point and 32-bit floating-point. these DSPs possess the ope
3、rational,flexibility fo high-speed controllers and numerical capability of array precessors.,Combining these two qualities, the TMS320C processors are inexpen-sive alter_natves tu custom_fabracated VLSI and muiltchip bit _slice pro-cessore. The following characteristics make this family the ideal ch
4、oice for a wide range of processing applications:,1) Very flexible instruction set 2) Inherent operational flexibility 3) High-speed performence 4) Innovation, parallel architectural design 5) Cost_effectiveness,Today ,the TMS320C family consisits of 8 generations : the C1x, C1x, C2x ,C3x ,C5x and C
5、54x are fixed-point, the C3x and C4x are floating-point ,and the C8x is a multiprocessor. Source code is upward compatible from one fixed-point generation to the next fixed-point,generation,and from floating -point generation to the next floating-point generation.,Upward compatibility preserves the
6、software generation of your investment, thereby providing a convenient and cost-efficient means to a higher-performance, more versatile DSP system.,Each generation of TMS320 devices has a CPU and a variety of on_chip memory and peripheral configurations for developing spin-off deveces. These spin-of
7、f devices satisfy a wide range of needs in the worldwide electronics market. When memory and peripherals are integrated into one processor, the overall system cost is greatly reduced, and ciecuit board space is saved.,The TMS320C family of DSPs offers better, ,more adaptable approach-es to tradition
8、al signal processing problems, such as filtering ,and error coding .Furthermore ,the TMS320C family supports conplex applications that often require multiple operations of the TMS320 family.,The operational flexibility and speed of the C5x are the result of combining an advanced Harvard architecture
9、(which has separate buses for program memory and data memory), a CPU with application-specific hardware logic , on-chip peripherals ,on-chip memory, and a highly specialized instruction set. The C5x is designed up to 50MIPS. Spin_off,devices that combine the C5x CPU with customized on-chip memory an
10、d peripheral configurations may be developed for special applications in the worldwide electronics market.,The C5x devices offer these advantages: 1 Enhanced TMS320 architectural design for increased performance and versatililty.,2 Modular architectural design for fast development of spin-off devece
11、s,3 Advanced integrated-circuit processing technology for increased performance and low power consumption.,4 Source code compatibility with C1x, C2x, and C2xx DSPs for fast and easy performance upgrades,5 Enhanced instruction set for faster algorithms and for optimized hige-level language operation,
12、6 Reduced power comsumption and increased radiation hardness because of new static design technuques.,The following tables list the capacity of on-chip RAM and ROM ,number,and type of series ports,3 Key features of the C5x DSP,Power 3.3V and 5V static CMOS technology with two power-down modes Power
13、consumption control with IDLE2 and IDLE instructions for power-down modes,Memory224K-word16-bit maximum addressable external memory space (64K-word16-bit paogram , 64K-word16-bit data, 64K-word16-bit I/O, and 32K-word16-bit global memory,Central Processing Unit(CPU) Central arithmetic logic unit(CAL
14、U) consisting of the following: 32-bit arithemtics logic units(ALU),32-bit accumulatou(ACC), and 32-bit accumulator buffer(ACCB),0 to 16-bit left and right data shifers and a 64-bit incremental data shifter 0 to 16-bit parallel logic unit(PLU) Dedicated auxiliary register arithmetic unit (ARAU) for
15、indirect addressing Eight Auxiliary registers,Program Control 8-level hardware stack 4_deep pipelined operation for delayed branch,call,and return instructions Eleven shadow registers for storing strategic CPU_controlled registers during an interrupt service routine,Instruction Set Single _cycle mul
16、tiply/accumulate instrutions Single-instruction repeat and block repeat operations Block memory move instructions for better program and data management Memory_mapper register load and store instructions,Conditional branch and call instructions Delayerd execution of branch and call instructions Fast
17、 return from interrupt instructions Index_addressing mode Bit-reversed Index_addressing mode for radix-3 fast_Fourier transforms(FFTS),On-chip Peripherals 64K parallel I/o ports(16 I/O ports are memory-mapped) Sixteen software-programmable wait-state generators for progam, data,I/O memory spaces Int
18、erval timer with period ,control, and counter registers for software stop, start and reset Phase-locked loop (PLL) clock generator with internal oscillator or external clock source Full_duplex synchronous series port interface for direct communication between the C5x and another serial device,Timing
19、-division multiplexde (TDM) series port Buffered series port(BSP) 8-bit parallel host port interface(HPI),4 Architectural Overview,The section provides an overview of architectural structure of the C5x,which consists of the buses ,on-chip memory,central processing unit(CPU), and on-chip peripherals.
20、 The C5x use an advanced .modified Harvard-type architecture and maximizes processing power with separate buses for program and data memory. The instrution set supports data transfer between the two memory spaces.,4.1 Bus structure,Separate program and data buses allow simultaneous access to program
21、 instruction and data, providing a high degree of parallelism. For example, while data is multiplied ,a previous product can be loaded into, added to, or subtracted from the accumulator and ,at the same time, a new address can be generator.,CPU,I/O PORT,ROM,Series Port,RAM,Paralled Port,Off-chip MEM
22、ORY,AB,DB,Von Neuman Struct,外部管理数据总线,外部管理地址总线,数据总线,数据地址总线,程序数据总线,程序地址总线,4.2 Central Processing Unit,The C5x CPU consists of these elements: Central Arithemetic Logic Unit(CALU) Parallel Logic Unit(PLU) Auxiliary Register Arithemetic Unit(ARRU) Memory-mapped Registers Program controller,Central Arithemetic Logic Unit(CALU),
