1、 GL850G USB 2.0 HUB Controller Datasheet Revision 1.04 Aug. 08, 2007 Genesys Logic, Inc. GL850G USB 2.0 Low-Power HUB Controller 2000-2007 Genesys Logic Inc. - All rights reserved. Page 2 Copyright: Copyright 2007 Genesys Logic Incorporated. All rights reserved. No part of the materials may be repro
2、duced in any form or by any means without prior written consent of Genesys Logic, Inc. Disclaimer: ALL MATERIALS ARE PROVIDED “AS IS” WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NO LICENSE OR RIGHT IS GRANTED UNDER ANY PATENT OR TRADEMARK OF GENESYS LOGIC INC GENESYS LOGIC HEREBY DISCLAIMS ALL
3、WARRANTIES AND CONDITIONS IN REGARD TO MATERIALS, INCLUDING ALL WARRANTIES, IMPLIED OR EXPRESS, OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF INTELLECTUAL PROPERTY. IN NO EVENT SHALL GENESYS LOGIC BE LIABLE FOR ANY DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES RESU
4、LTING FROM LOSS OF INFORMATION OR PROFITS. PLEASE BE ADVISED THAT THE MATERIALS MAY CONTAIN ERRORS OR OMMISIONS. GENESYS LOGIC MAY MAKE CHANGES TO THE MATERIALS OR TO THE PRODUCTS DESCRIBED THEREIN AT ANY TIME WITHOUT NOTICE. Trademarks: is a registered trademark of Genesys Logic, Inc. All trademark
5、s are the properties of their respective owners. Office: Genesys Logic, Inc. 12F, No. 205, Sec. 3, Beishin Rd., Shindian City, Taipei, Taiwan Tel: (886-2) 8913-1888 Fax: (886-2) 6629-6168 http:/ GL850G USB 2.0 Low-Power HUB Controller 2000-2007 Genesys Logic Inc. - All rights reserved. Page 3 Revisi
6、on History Revision Date Description 1.00 05/10/2006 First formal release 1.01 08/30/2006 Updated DC Supply Current, Table6.6, P.23 1.02 11/03/2006 Modify 93C46 Configuration, Table 5.1, P.19 1.03 01/17/2007 Modify Table 6.1-Maximum Ratings, P.21 1.04 08/08/2007 Modify Table 6.6-DC Supply Current, P
7、.23 GL850G USB 2.0 Low-Power HUB Controller 2000-2007 Genesys Logic Inc. - All rights reserved. Page 4 TABLE OF CONTENTS CHAPTER 1 GENERAL DESCRIPTION. 7 CHAPTER 2 FEATURES 8 CHAPTER 3 PIN ASSIGNMENT 9 3.1 PINOUTS 9 3.2 PIN LIST 10 3.3 PIN DESCRIPTIONS . 10 CHAPTER 4 BLOCK DIAGRAM 13 CHAPTER 5 FUNCT
8、ION DESCRIPTION. 14 5.1 GENERAL 14 5.2 CONFIGURATION AND I/O SETTINGS. 16 CHAPTER 6 ELECTRICAL CHARACTERISTICS. 21 6.1 MAXIMUM RATINGS. 21 6.2 OPERATING RANGES 21 6.3 DC CHARACTERISTICS 21 6.4 POWER CONSUMPTION 23 CHAPTER 7 PACKAGE DIMENSION. 24 CHAPTER 8 ORDERING INFORMATION 25 GL850G USB 2.0 Low-P
9、ower HUB Controller 2000-2007 Genesys Logic Inc. - All rights reserved. Page 5 LIST OF FIGURES FIGURE 3.1GL850G 48 PIN LQFP PINOUT DIAGRAM. 9 FIGURE 4.1 GL850G BLOCK DIAGRAM (SINGLE TT) . 13 FIGURE 5.1 OPERATING IN USB 1.1 SCHEME. 15 FIGURE 5.2 OPERATING IN USB 2.0 SCHEME. 16 FIGURE 5.3 POWER ON SEQ
10、UENCE OF GL850G. 17 FIGURE 5.4 TIMING OF PGANG/SUSPEND STRAPPING 17 FIGURE 5.5 INDIVIDUAL/GANG MODE SETTING 18 FIGURE 5.6 SELF/BUS POWER SETTING 18 FIGURE 5.7 LED CONNECTION 19 FIGURE 5.8 SCHEMATICS BETWEEN GL850G AND 93C46 20 FIGURE 7.1 GL850G 48 PIN LQFP PACKAGE. 24 GL850G USB 2.0 Low-Power HUB Co
11、ntroller 2000-2007 Genesys Logic Inc. - All rights reserved. Page 6 LIST OF TABLES TABLE 3.1GL850G 48 PIN LIST 10 TABLE 3.3 - PIN DESCRIPTIONS . 10 TABLE 5.1 93C46 CONFIGURATION . 19 TABLE 6.1 MAXIMUM RATINGS 21 TABLE 6.2 OPERATING RANGES . 21 TABLE 6.3 DC CHARACTERISTICS EXCEPT USB SIGNALS 21 TABLE
12、 6.4 DC CHARACTERISTICS OF USB SIGNALS UNDER FS/LS MODE . 22 TABLE 6.5 DC CHARACTERISTICS OF USB SIGNALS UNDER HS MODE 22 TABLE 6.6 DC SUPPLY CURRENT . 23 TABLE 8.1 ORDERING INFORMATION. 25 GL850G USB 2.0 Low-Power HUB Controller 2000-2007 Genesys Logic Inc. - All rights reserved. Page 7 CHAPTER 1 G
13、ENERAL DESCRIPTION GL850G is Genesys Logics advanced version Hub solutions which fully comply with Universal Serial Bus Specification Revision 2.0. GL850G embeds an 8-bit RISC processor to manipulate the control/status registers and respond to the requests from USB host. Firmware of GL850G will cont
14、rol its general purpose I/O (GPIO) to access the external EEPROM and then respond to the host the customized PID and VID configured in the external EEPROM. Default settings in the internal mask ROM is responded to the host without having external EEROM. GL850G is designed for customers with much fle
15、xibility. The more complicated settings such as PID, VID, and number of downstream ports settings are easily achieved by programming the external EEPROM (Ref. to Chapter 5). Each downstream port of GL850G supports two-color (green/amber) status LEDs to indicate normal/abnormal status. GL850G also su
16、pport both Individual and Gang modes (4 ports as a group) for power management. The GL850G is a full function solution which supports both Individual/Gang power management modes and the two-color (green/amber) status LEDs. Please refer the table in the end of this chapter for more detail. To fully m
17、eet the cost/performance requirement, GL850G is a single TT hub solution for the cost requirement. Genesys Logic also provides GL852 for multiple TT hub solution to target on systems which require higher performance for full/low-speed devices, like docking station, embedded system etc Please refer t
18、o GL852 datasheet for more detailed information. *TT (transaction translator) is the main traffic control engine in an USB 2.0 hub to handle the unbalanced traffic speed between the upstream port and the downstream ports. GL850G USB 2.0 Low-Power HUB Controller 2000-2007 Genesys Logic Inc. - All rig
19、hts reserved. Page 8 CHAPTER 2 FEATURES Compliant to USB specification Revision 2.0 Support 4/3/2 downstream ports by I/O pin configuration Upstream port supports both high-speed (HS) and full-speed (FS) traffic Downstream ports support HS, FS, and low-speed (LS) traffic 1 control pipe (endpoint 0,
20、64-byte data payload) and 1 interrupt pipe (endpoint 1, 1-byte data payload) Backward compatible to USB specification Revision 1.1 On-chip 8-bit micro-processor RISC-like architecture USB optimized instruction set Performance: 6 MIPS 12MHz With 64-byte RAM and 2K mask ROM Support customized PID, VID
21、 by reading external EEPROM Support downstream port configuration by reading external EEPROM Single Transaction Translator (STT) Single TT shares the same TT control logics for all downstream port devices. This is the most cost effective solution for TT. Multiple TT provides individual TT control lo
22、gics for each downstream port. This is a performance better choice for USB 2.0 hub. Please refer to GL852 datasheet for more detailed information. Integrate USB 2.0 transceiver Each downstream port supports two-color status indicator, with automatic and manual modes compliant to USB specification Re
23、vision 2.0 Built-in upstream 1.5K pull-up and downstream 15K pull-down Embed serial resister for USB signals Support both individual and gang modes of power management and over-current detection for downstream ports Conform to bus power requirements Automatic switching between self-powered and bus-p
24、owered modes Support compound-device (non-removable in downstream ports) by I/O pin configuration Configurable non-removable device support PLL embedded with external 12 MHz crystal Embeds 5V to 3.3V regulator Low power consumption Improve output drivers with slew-rate control for EMI reduction Inte
25、rnal power-fail detection for ESD recovery Full function in 48-pin LQFP package Applications: Stand-alone USB hub PC motherboard USB hub, Docking of notebook LCD monitor hub Any compound device to support USB HUB function GL850G USB 2.0 Low-Power HUB Controller 2000-2007 Genesys Logic Inc. - All rig
26、hts reserved. Page 9 CHAPTER 3 PIN ASSIGNMENT 3.1 Pinouts GL850GLQFP - 48AVDD1AGND2DM03DP04DM15DP16AVDD7AGND8DM29DP210RREF11AVDD12PAMBER2PGREEN2DVDDPAMBER3PGREEN3PWREN3#OVCUR3#PWREN4#OVCUR4#TESTRESET#DVDD36 35 34 33 32 31 30 29 28 27 26 25PSELF 37DVDD 38PGANG 39OVCUR2# 40PWREN2# 41OVCUR1# 42PWREN1#
27、43DVDD 44PGREEN1 45PAMBER1 46V5 47V33 48PAMBER4PGREEN4DP4DM4AGNDAVDDDP3DM3AVDDX2X1AGND242322212019181716151413Figure 3.1g1025GL850G 48 Pin LQFP Pinout Diagram GL850G USB 2.0 Low-Power HUB Controller 2000-2007 Genesys Logic Inc. - All rights reserved. Page 10 3.2 Pin List Table 3.1g1025GL850G 48 Pin
28、List Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type 1 AVDD P 13 AGND P 25 DVDD P 37 PSELF I_5V 2 AGND P 14 X1 I 26 RESET# I_5V 38 DVDD P 3 DM0 B 15 X2 O 27 TEST I 39 PGANG B 4 DP0 B 16 AVDD P 28 OVCUR4# I_5V 40 OVCUR2# I_5V 5 DM1 B 17 DM3 B 29 PWREN4# O 41 PWREN2# O 6 DP
29、1 B 18 DP3 B 30 OVCUR3# I_5V 42 OVCUR1# I_5V 7 AVDD P 19 AVDD P 31 PWREN3# O 43 PWREN1# O 8 AGND P 20 AGND P 32 PGREEN3 O 44 DVDD P 9 DM2 B 21 DM4 B 33 PAMBER3 O 45 PGREEN1 O 10 DP2 B 22 DP4 B 34 DVDD P 46 PAMBER1 O 11 RREF B 23 PGREEN4 O 35 PGREEN2 B 47 V5 P 12 AVDD P 24 PAMBER4 O 36 PAMBER2 O 48 V
30、33 P 3.3 Pin Descriptions Table 3.3 - Pin Descriptions USB Interface GL850G Pin Name 48Pin# I/O Type Description DM0,DP0 3,4 B USB signals for USPORT DM1,DP1 5,6 B USB signals for DSPORT1 DM2,DP2 9,10 B USB signals for DSPORT2 DM3,DP3 17,18 B USB signals for DSPORT3 DM4,DP4 21,22 B USB signals for D
31、SPORT4 RREF 11 B A 680 resister must be connected between RREF and analog ground (AGND). Note: USB signals must be carefully handled in PCB routing. For detailed information, please refer to GL850G Design Guideline. GL850G USB 2.0 Low-Power HUB Controller 2000-2007 Genesys Logic Inc. - All rights re
32、served. Page 11 HUB Interface GL850G Pin Name 48Pin# I/O Type Description OVCUR14# 42,40, 30,28 I_5V (pu) Active low. Over current indicator for DSPORT14 OVCUR1# is the only over current flag for GANG mode. PWREN14# 43,41, 31,29 O Active low. Power enable output for DSPORT14 PWREN1# is the only powe
33、r-enable output for GANG mode. PGREEN14 45,35, 32,23 1,3,4:O 2:B (pd) Green LED indicator for DSPORT14 *GREEN12 are also used to access the external EEPROM For detailed information, please refer to Chapter 5. PAMBER14 46,36, 33,24 O (pd) Amber LED indicator for DSPORT14 *Amber12 are also used to acc
34、ess the external EEPROM For detailed information, please refer to Chapter 5. PSELF 37 I_5V 0: GL850G is bus-powered. 1: GL850G is self-powered. PGANG 39 B This pin is default put in input mode after power-on reset. Individual/gang mode is strapped during this period. After the strapping period, this
35、 pin will be set to output mode, and then output high for normal mode. When GL850G is suspended, this pin will output low. *For detailed explanation, please see Chapter 5 Gang input:1, output: 0normal, 1suspend Individual input:0, output: 1normal, 0suspend Clock and Reset Interface GL850G Pin Name 4
36、8Pin# I/O Type Description X1 14 I 12MHz crystal clock input. X2 15 O 12MHz crystal clock output. RESET# 26 I_5V Active low. External reset input, default pull high 10K. When RESET# = low, whole chip is reset to the initial state. System Interface GL850G Pin Name 48Pin# I/O Type Description TEST 27
37、I (pd) 0: Normal operation. 1: Chip will be put in test mode. Power / Ground GL850G Pin Name 48Pin# I/O Type Description AVDD 1,7,12, 16,19 P 3.3V analog power input for analog circuits. AGND 2,8,13, 20 P Analog ground input for analog circuits. GL850G USB 2.0 Low-Power HUB Controller 2000-2007 Gene
38、sys Logic Inc. - All rights reserved. Page 12 DVDD 25,34, 38,44 P 3.3V digital power input for digital circuits V5 47 P 5V-to-3.3V regulator Vin V33 48 P 5V-to-3.3V regulator Vout Note: Analog circuits are quite sensitive to power and ground noise. PCB layout must take care the power routing and the
39、 ground plane. For detailed information, please refer to GL850G Design Guideline. Notation: Type O Output I Input I_5V 5V tolerant input B Bi-directional B/I Bi-directional, default input B/O Bi-directional, default output P Power / Ground A Analog SO Automatic output low when suspend pu Internal pu
40、ll up pd Internal pull down odpu Open drain with internal pull up GL850G USB 2.0 Low-Power HUB Controller 2000-2007 Genesys Logic Inc. - All rights reserved. Page 13 CHAPTER 4 BLOCK DIAGRAM FRTIMERUSPORTTransceiverRAMCPUControl/StatusRegisterUTMIUSPORTLogicSIED+ D-GPIOREPEATERREPEATER / TT Routing L
41、ogicDSPORT1 Logic DSPORT2 Logic DSPORT3 Logic DSPORT4 LogicDSPORTTransceiverDSPORT DSPORT DSPORT12MHzD+ D- LED/OVCUR/PWRENBD+ D- LED/OVCUR/PWRENBD+ D- LED/OVCUR/PWRENBD+ D- LED/OVCUR/PWRENBTT (Transaction Translator)PLLx40, x10Transceiver Transceiver TransceiverROMFigure 4.1 GL850G Block Diagram (si
42、ngle TT) GL850G USB 2.0 Low-Power HUB Controller 2000-2007 Genesys Logic Inc. - All rights reserved. Page 14 CHAPTER 5 FUNCTION DESCRIPTION 5.1 General 5.1.1 USPORT Transceiver USPORT (upstream port) transceiver is the analog circuit that supports both full-speed and high-speed electrical characteri
43、stics defined in chapter 7 of USB specification Revision 2.0. USPORT transceiver will operate in full-speed electrical signaling when GL850G is plugged into a 1.1 host/hub. USPORT transceiver will operate in high-speed electrical signaling when GL850G is plugged into a 2.0 host/hub. 5.1.2 PLL (Phase
44、 Lock Loop) GL850G contains a 40x PLL. PLL generates the clock sources for the whole chip. The generated clocks are proven quite accurate that help in generating high speed signal without jitter. 5.1.3 FRTIMER This module implements hub (micro)frame timer. The (micro)frame timer is derived from the
45、hubs local clock and is synchronized to the host (micro)frame period by the host generated Start of (micro)frame (SOF). FRTIMER keeps tracking the hosts SOF such that GL850G is always safely synchronized to the host. The functionality of FRTIMER is described in section 11.2 of USB Specification Revi
46、sion 2.0. 5.1.4 C C is the micro-processor unit of GL850G. It is an 8-bit RISC processor with 2K ROM and 64 bytes RAM. It operates at 6MIPS of 12Mhz clock to decode the USB command issued from host and then prepares the data to respond to the host. In addition, C can handle GPIO (general purpose I/O
47、) settings and reading content of EEPROM to support high flexibility for customers of different configurations of hub. These configurations include self/bus power mode setting, individual/gang mode setting, downstream port number setting, device removable/non-removable setting, and PID/VID setting.
48、5.1.5 UTMI (USB 2.0 Transceiver Macrocell Interface) UTMI handles the low level USB protocol and signaling. Its designed based on the Intels UTMI specification 1.01. The major functions of UTMI logic are to handle the data and clock recovery, NRZI encoding/decoding, Bit stuffing /de-stuffing, suppor
49、ting USB 2.0 test modes, and serial/parallel conversion. 5.1.6 USPORT logic USPORT implements the upstream port logic defined in section 11.6 of USB specification Revision 2.0. It mainly manipulates traffics in the upstream direction. The main functions include the state machines of Receiver and Transmitter, interfaces between UTMI and SIE, and traffic control t
