1、Hardware SpecificationPCI eXtensions for InstrumentationAn Implementation of PXI Hardware Specification Rev. 2.2 09/22/2004Revision 2.2 September 22, 2004PXI Hardware Specification Rev. 2.2 09/22/2004 ii www.pxisa.orgIMPORTANT INFORMATIONCopyright Copyright 1997 2004 PXI Systems Alliance. All rights
2、 reserved.This document is copyrighted by the PXI Systems Alliance. Permission is granted to reproduce and distribute this document in its entirety and without modification.NOTICEThe PXI Hardware Specification is authored and copyrighted by the PXI Systems Alliance. The intent of the PXI Systems All
3、iance is for the PXI Hardware Specification to be an open industry standard supported by a wide variety of vendors and products. Vendors and users who are interested in developing PXI-compatible products or services, as well as parties who are interested in working with the PXI Systems Alliance to f
4、urther promote PXI as an open industry standard are invited to contact the PXI Systems Alliance for further information.The PXI Systems Alliance wants to receive your comments on this specification. Visit the PXI Systems Alliance web site at http:/www.pxisa.org/ for contact information and to learn
5、more about the PXI Systems Alliance.The attention of adopters is directed to the possibility that compliance with or adoption of the PXI Systems Alliance specifications may require use of an invention covered by patent rights. The PXI Systems Alliance shall not be responsible for identifying patents
6、 for which a license may be required by any PXI Systems Alliance specification, or for conducting legal inquiries into the legal validity or scope of those patents that are brought to its attention. PXI Systems Alliance specifications are prospective and advisory only. Prospective users are responsi
7、ble for protecting themselves against liability for infringement of patents.The information contained in this document is subject to change without notice. The material in this document details a PXI Systems Alliance specification in accordance with the license and notices set forth on this page. Th
8、is document does not represent a commitment to implement any portion of this specification in any companys products.The PXI Systems Alliance makes no warranty of any kind with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particul
9、ar purpose. The PXI Systems Alliance shall not be liable for errors contained herein or for incidental or consequential damages in connection with the furnishing, performance, or use of this material.Compliance with this specification does not absolve manufacturers of PXI equipment from the requirem
10、ents of safety and regulatory agencies (UL, CSA, FCC, IEC, etc.).TrademarksPXIis a trademark of the PXI Systems Alliance.PICMGand CompactPCIare trademarks of the PCI Industrial Computation Manufacturers Group.Product and company names are trademarks or trade names of their respective companies. PXI
11、Systems Alliance iii PXI Hardware Specification Rev. 2.2 09/22/2004PXI Specification Revision HistoryThis section is an overview of the revision history of the PXI specification. Revision 1.0, August 20, 1997This is the first public revision of the PXI specification.Revision 2.0, July 28, 2000This r
12、evision incorporates changes that include but are not limited to the following:Transfer of the specification ownership to the PXI System Alliance.Modification of pin assignment to comply with PICMG 2.0 R3.0 that include addition of GA0-GA4 signals to all slots, removal of PRST#, DEG#, and FAL# from
13、peripheral slots, addition of IPMB bus to all slots, addition of HEALTHY# to all slots, addition of SMB bus to system slot, addition of BD_SEL# to peripheral slots, changing SYSEN# to UNC on peripheral slots, and changing IDSEL to GND on system slot.Removal of references to Serialized IRQ due to PIC
14、MG 2.0 R3.0 adoption.Addition of 66MHz PCI operation.Removal of J5 as a reserved connector.Allowance of J5 to be populated only in custom PXI boards and backplanes that are offered as a system.Allowance for star trigger routings other than only peripheral slots in first two segments in PXI backplane
15、s with more than two segments.Allowance for the local bus to be routed between segments.Addition of rules about connecting the IDSEL lines of first segment PCI devices, bridges, and peripheral slots to AD25:31 and routing peripheral slot INT lines to system slot INT lines based on the peripheral slo
16、t IDSEL to AD25:31 connection.Increased required current on 3.3V for a 5V backplane to comply with requirement of 3.3V being available according to PICMG 2.0 R3.0Addition of Windows 98 and Windows 2000 software frameworks.Removal of requirements for PC 9X compliance for controllers and peripherals.A
17、ddition of segment divider glyph.Removal of SHALL NOT rule for chassis ground to digital ground connection and addition of SHOULD NOT recommendation for chassis ground to digital ground.Modification of requirements for EMC that includes changing IEC 61326-1:1997 to IEC 61326?1:1998 and IEC CISPR-11
18、to EN5501.Addition of maximum Voh and minimum Vol values for trigger bus.Modification of the legal notice.Addition of license requirement for use of the PXI logo.Revision 2.1, February 4, 2003This revision incorporates changes that include but are not limited to the following:Removal of software rel
19、ated rules (Refer to the now separate PXI Software Specification).Removal of J4 as a reserved connector.Addition of rules associated with 6U chassis that support stacking of two 3U modules in a single 6U slot.Addition of a rule that limits the maximum number of slots in a chassis to 31.Combining the
20、 chassis power supply minimum power requirements tables into one table and removing the recommended current entries in favor of required current entries.PXI Hardware Specification Rev. 2.2 09/22/2004 iv www.pxisa.orgIncreasing the -12V required current.Addition of the minimum current-handling requir
21、ement for each slot.Turning the recommendation that modules document their required current into a rule.Addition of a recommendation to limit the maximum power that a module dissipates within a chassis.Addition of a rule that requires filler panels to be installed in chassis slots that are not popul
22、ated.Addition of an implementation note that recommends not mapping a modules registers mapped to PCI I/O Space.Modification of J2/P2 B19 and J2/P2 B21 pin assignments from GND to RSV on star trigger and peripheral pinouts.Revision 2.2, September 22, 2004This revision incorporates changes that inclu
23、de but are not limited to the following:Addition of a chassis class that does not support 64-bit PCI and allowance of controllers used in such a chassis to implement rear I/O.Addition of a low power chassis class that reduces the minimum power requirements.Addition of module grounding recommendation
24、sAddition of rules for 5V tolerance for PXI_CLK10 and PXI_CLK10_IN Addition of pull-up resistor requirements for the PXI_CLK10_IN signal.Addition of recommendation not to use low cost PLLs for PXI_CLK10 distributionAddition of an observation on circuit operation for transitioning between clock sourc
25、es.Addition of a recommendation for modules using triggers to connect to all 8 triggersAddition of a rule that the pull-up on the PXI_STAR line be 20K Ohm or greater.Addition of a rule that puts requirements on the disabling of external 10 MHz clock sources. PXI Systems Alliance v PXI Hardware Speci
26、fication Rev. 2.2 09/22/2004Contents1. Introduction1.1 Objectives 11.2 Intended Audience and Scope. 21.3 Background and Terminology. 21.4 Applicable Documents 31.5 Useful Web Sites. 42. PXI Architecture Overview2.1 Mechanical Architecture Overview 52.1.1 Chassis Supporting Stacking 3U Modules in a 6
27、U Slot 62.1.2 System Slot Location 72.1.3 Additional Mechanical Features 82.1.4 Interoperability with CompactPCI 82.2 Electrical Architecture Overview 82.2.1 Peripheral Component Interconnect (PCI) Features . 92.2.2 Local Bus. 92.2.3 System Reference Clock . 102.2.4 Trigger Bus 102.2.5 Star Trigger
28、. 102.2.6 System Expansion with PCI-PCI Bridge Technology 112.2.7 32-bit PCI and Rear I/O 112.3 Software Architecture Overview. 123. Mechanical Requirements3.1 CompactPCI Mechanical Requirements . 133.2 Maximum Number of Slots. 133.3 System Slot Location and Rules . 133.4 Logos and Compatibility Gly
29、phs 143.5 Slot Numbering for 6U Chassis that Support 3U Stacking. 153.6 Environmental Testing 173.7 Cooling Specifications 173.7.1 Plug-in Module Requirements 173.7.2 Chassis Requirements . 183.8 Chassis and Module Grounding Requirements and EMI Guidelines . 183.9 Regulatory Requirements 183.9.1 Req
30、uirements for EMC . 183.9.2 Requirements for Electrical Safety . 193.9.3 Additional Requirements for Chassis 194. Electrical Requirements4.1 PXI Signal Groups 204.1.1 P1/J1: Signals 204.1.2 P2/J2: Signals 204.1.2.1 Signals from CompactPCI 64-bit Connector Specification. 214.1.2.2 PXI Bused Reserved
31、Signals . 224.1.2.3 Local Buses 224.1.2.4 Reference Clock: PXI_CLK10 244.1.2.5 Trigger Bus 254.1.2.6 Star Trigger 294.1.3 Electrical Guidelines for 6U 314.1.3.1 6U Peripheral Module Connector Population 314.1.3.2 6U Chassis that Support Stacking 3U Modules. 31ContentsPXI Hardware Specification Rev.
32、2.2 09/22/2004 vi www.pxisa.org4.2 Connector Pin Assignments (J1/P1 and J2/P2). 324.2.1 General Peripheral Slots 324.2.2 System Slot 344.2.3 Star Trigger Slot 364.3 Chassis Power Supply Specifications . 384.3.1 Low Power Chassis Power Supply Specifications 394.4 PXI Module Ground Connections. 405. P
33、XI Software Specification Compliance6. PXI 32-bit6.1 32-bit PCI Only General Peripheral Slots. 446.2 Rear I/O System Slot. 466.3 32-bit PCI Only Star Trigger Slot . 48FiguresFigure 1-1. The PXI Architecture . 2Figure 2-1. PXI Peripheral Module Form Factors and Connectors 5Figure 2-2. Example of a 33
34、 MHz 3U PXI System (Single Bus Segment) 6Figure 2-3. Example of a 6U Chassis that Supports Stacking 3U Modules . 7Figure 2-4. PXI and CompactPCI Interoperability. 8Figure 2-5. PXI Local Bus Routing 10Figure 2-6. PXI Trigger Architecture for Two Bus Segments 11Figure 3-1. Example of PXI Slot Designat
35、ions for a Chassis. 14Figure 3-2. PXI Logo 15Figure 3-3. Star Trigger Slot Glyph 15Figure 3-4. PCI Segment Divider Glyph 15Figure 3-5. Example of Slot Numbering for a 6U Chassis that Supports 3U Stacking 16Figure 3-6. Cooling Airflow Direction in a PXI System 17Figure 4-1. PXI Asynchronous Trigger T
36、iming . 25Figure 4-2. Synchronous Trigger Timing . 26Figure 4-3. PXI Trigger Bus Termination 27Figure 4-4. Text Required for Low Power Chassis 40Figure 4-5. Power and Ground Connections on a PXI Module . 40Figure 6-1. Text Required for Rear I/O Chassis 43TablesTable 4-1. Local Bus Routings 23Table 4
37、-2. PXI Asynchronous Trigger Timing Parameters. 25Table 4-3. PXI Synchronous Trigger Timing 26Table 4-4. DC Specifications. 28Table 4-5. Pull-Up Resistor Values. 28Table 4-6. Type A, High Current Driver, AC Specifications 28Table 4-7. Star Trigger Mapping. 29Table 4-8. PXI System Signal Groups. 32Ta
38、ble 4-9. Generic Peripheral Slot Pinout. 33Table 4-10. System Slot Pinout . 35Table 4-11. Star Trigger Slot Pinout . 37Table 4-12. PXI Chassis Power Supply Minimum Power Requirements . 38Table 4-13. Minimum Current Handling Per Slot. 39Table 4-14. Low Power PXI Chassis Power Supply Minimum Power Req
39、uirements 39Table 6-1. 32-bit PCI Only Generic Peripheral Slot Pinout 45Table 6-2. Rear I/O System Slot Pinout 47Table 6-3. 32-bit PCI Only Star Trigger Slot Pinout. 49Contents PXI Systems Alliance vii PXI Hardware Specification Rev. 2.2 09/22/2004 PXI Systems Alliance 1 PXI Hardware Specification R
40、ev. 2.2 09/22/20041. IntroductionThis section describes the primary objectives and scope of the PCI eXtensions for Instrumentation (PXI) specification. It also defines the intended audience and lists relevant terminology and documents. 1.1 ObjectivesPXI was created in response to the needs of a vari
41、ety of instrumentation and automation users who require ever increasing performance, functionality, and reliability from compact rugged systems that are easy to integrate and use. Existing industry standards are leveraged by PXI to benefit from high component availability at lower costs. Most import
42、antly, by maintaining software compatibility with industry-standard personal computers, PXI allows industrial customers to use the same software tools and environments with which they are familiar. PXI leverages the electrical features defined by the widely adopted Peripheral Component Interconnect
43、(PCI) specification. It also leverages the CompactPCI form factor, which combines the PCI electrical specification with rugged Eurocard mechanical packaging and high-performance connectors. This combination allows CompactPCI and PXI systems to have up to seven peripheral slots versus four in a deskt
44、op PCI system. Systems with more expansion slots can be built by using multiple bus segments with industry-standard PCI-PCI bridges. For example, a 13-slot PXI system can be built using a single PCI-PCI bridge. The PXI Hardware Specification adds electrical features that meet the high-performance re
45、quirements of instrumentation applications by providing triggering, local buses, and system clock capabilities. PXI also offers two-way interoperability with CompactPCI products.By implementing desktop PCI in a rugged form factor, PXI systems can leverage the large base of existing industry-standard
46、 software. Desktop PC users have access to different levels of software, from operating systems to low-level device drivers to high-level instrument drivers to complete graphical APIs. All of these software levels can be used in PXI systems. The PXI Systems Alliance maintains a separate Software Spe
47、cification for PXI modules, chassis, and systems. By having a separate Software Specification, the PXI Systems Alliance can more quickly adopt the latest operating systems and software standards. PXI modules, chassis, and systems developed to comply with this PXI Hardware Specification must also com
48、ply with the PXI Software Specification.1. IntroductionPXI Hardware Specification Rev. 2.2 09/22/2004 2 www.pxisa.orgFigure 1-1 summarizes the scope of the PXI specification standard by depicting its mechanical, electrical, and software architectures. It also shows how the separate Hardware and Soft
49、ware specifications are partitioned.Figure 1-1. The PXI Architecture1.2 Intended Audience and ScopeThis specification is organized with a top-down approach whereby general descriptions precede the more detailed specifications found deeper in the subsections. This structure is intended to serve the needs of a variety of audiences from product developers to system integrators to end-users. Product developers may want to become familiar with all portions of this specification while end users may be interested in only the feature set description and perhaps the summaries of how th
