1、第八章,功能验证,Outlines,What is Verification? Problem and Trend of Function Verification HW/SW Co-verification Emulator based co-verification ESL design tool based co-verification Assertion Based Verification (ABV),What is Verification?,Design concept verification (functionality verification) Does the beh
2、avioral idea work as expected? Design implementation verification Does the physical design behave as expected? Design performance verification How fast the chip can operate correctly? How much power the chip consumes? Fault simulation Will the selected test vector cover design and manufacturing faul
3、ts? Silicon chip testing Does the silicon chip work and operate as expected?,Problem of Function Verification,Functionality Verification has been over 60% (even 70%) of design cycle for millions gates design. 30% -70% manpower for verification CPU time increases exponentially in big design,Most of t
4、he verification time is spent doing debug Hardware/software interactions Analog/digital interactions Testbenchs IC design focus on RTL verification onlySoftware development after IC is ready Verification can never finished! (example: a chip from CL company, ARM+DSP Based Portable Audio Decoder, spen
5、d 3 yrs design, tapeout 6 times, but never on production),Trend of Function Verification,New methodologies and better tools Understand system context Hardware/software co-verification Locate root cause of problems easily Assertion based verification,Outlines,What is Verification? Problem and Trend o
6、f Function Verification HW/SW Co-verification Emulator based co-verification ESL design tool based co-verification Assertion Based Verification (ABV) Methodology,Hardware/Software Co-verification,System components Not just Hardware RTOS Software Analog Environment Verification of complete system bot
7、h HW/SW,Hardware/Software Co-verification,HW/SW co-verification is a methodology that enables the execution of embedded system software on a simulated representation of the system hardware Emulator based co-verification (emulation) ESL based co-verification,Emulation,Emulation is a method of modelin
8、g the design in hardware Emulation dominated by FPGA-based system,Co-Emulation,Integrating simulation and emulation environments for co-verification. Providing an in-circuit verification environment. Providing a system-level testing environment. Providing a system prototyping.,Co-verification with E
9、SL Design tool,Done in early design stage More flexible Less expensive,Outlines,What is Verification? Problem and Trend of Functional Verification HW/SW Co-verification Emulator based co-verification ESL design tool based co-verification Assertion Based Verification (ABV) Methodology What is asserti
10、on Assertion in simulation Assertion in formal verification,Assertion Based Verification (ABV),Why need assertion based verification? What is assertion based verification?,Current Practices of Function Verification,HDL simulation where engineers write “reactive testbenches” Check waveform, code cove
11、rage, then write more patterns Input generation Manual (verification engineers think of test cases) Usually or block level verification Pseudo-random Need auto-testbench tool, need to have accurate model at abstract level Need input constraints to limit to legal vectors Normally for chip level verif
12、ication Mixed (some random parameters)Need to write a lot of vectors to get enough “coverage”!,Current Practices cont.,Low controllability (cant generate enough vectors). Low observability (internal errors might not propagate during test). Doesnt facilitate reuse.,Trend of Function Verification,Smar
13、ter simulation Properties, Accelerated simulator, coverage tool Static formal verification Start from reset state, looking for proof Dynamic formal verification (or model checking, property checking, hybrid formal verification) Start from simulation result, prove whether a property is hold under the
14、 simulation. Looking for counterexamples Assertion based verification methodology Assertions are statements about how the design is intended to behave at the RTL level or higher abstraction level simulation based verification Formal verification with advanced hybrid formal tool,Assertion-Based Verif
15、ication (ABV),Convergence of design and verification to create an improved design-for-verification methodology.,Assertion,Assertion is a precise description of what behavior is expected when a given input is presented to design. used as monitors/checker looking for bad behavior during verification u
16、sed to create an alert for desired behavior,Assertion Based Verification (AVB),Assertions must be written in design code (C like system abstraction model or RTL) or testbench (Establish assertions) as an enabler of much more efficient verification, simplified analysis, and the synergistic use of sim
17、ulation and formal verification methods.,Assertion in simulation Can be used as monitor, coverage analysis tool Assertion in formal verification (model checking) Can be used to write constraints of inputs and to write the property of the design,Assertion Languages in Industry,An assertion language:
18、standard assertion format and good tool support Open Vera Assertions Language (OVA) (Synopsys) Property Specification Language (PSL) (IBM, based on Sugar) Accelera Open Verification Library (OVL) SystemVerilog C or SystemC,Example: Properties Written in OVL,Design spec: After request condition (req)
19、 is asserted, an acknowledge (ack) must occur after 3 and before 7 clock cycles have occurred. Implementation:Using Open Verification Library (OVL) shows the verification of using assert_frame module in Verilog,Example: Properties Written in OVA,RTL for 8-bit counter:module counter_8bit(rst, clk, cn
20、t);input rst, clk;output 7:0 cnt;reg 7:0 counter;always (rst or posedge clk)if (rst)counter = 8b0;elsecounter = counter + 1;assign cnt = counter endmodule,Testbench to check counter overflow:unit counter_checker (logic clk, logic 7:0 counter) ; clock negedge (clk) event e_overflow : (cnt=8hff) #1 (c
21、nt=8h00); assert a_overflow : check (e_overflow); endunit bind module counter_8bit : counter_checker (clk, cnt) ;,Write abstract (behavior level) Assertion,Assertion implemented in C/SystemC: System level design Assertion implemented in RTL: Design engineers can embed assertion calls inline with the
22、ir RTL design. The assertions do not get synthesized. Assertion implemented in testbench: instantiate assertion calls in a testbench. Standard protocol: such AMBA, SDRAM, there maybe exists a checker types library (available assertion), just use it.,What need to be written as “assertion”?,What need
23、to be written as “assertion”? assertions about the properties according to the spec. assertions about the corner case. assertions about any worry case that may disobey the design intent Constrains for assertion are important Restrict the input vectors to be realistic constrains at the block level in
24、terface, also can be reused by other connected blocks, or as assertions in the chip level Without constraints, a formal engine will report false errors instead of design bugs.,Assertion Used in Simulation,Assertions used in simulation: Assertions were used to improve observability, which means the a
25、bility to observe bugs once they are triggered by a simulation vector. Itll speed bugging Without assertions, test vectors had to be much longer to ensure that triggered bugs were propagated to observable outputs, else the errors remained undetected. When manually generating the simulation vector, t
26、here is no need of input constrain in the whole flow, otherwise the constrain is rather important.,Assertion Used in Formal Verification,Model Checking Dynamic Formal Verification (Hybrid Analysis) Used at behavioral level after simulation is verified and the debug is modified. Starts with full DUT
27、states taken from normal simulation traces (“seeds”), hence the term “dynamic”.,Given a seed, for each assertion it uses an ultra-fast bounded model checking algorithm to exhaustively search for counterexamples that can be produced within a few cycles starting from the seed ,Dynamic Formal verificat
28、ion,Pros & Cons,Pros: Providing internal test points in the design Simplifying the diagnosis and detection of bugs by localizing the occurrence of a suspected bug to an assertion monitor Allowing designers to verify the same assertions using both simulation and formal verification Increasing observa
29、bility when simulation is used Increasing both controllability Save time to market (re-use: library, assertions) Cons: Need spend time on writing assertion Model checking tool not mature,Tools Needed,To be able to understand and analyze assertions and results, debug violations Simulation tool + form
30、al verification tool + view tool + coverage analyzer toolSynopsyss Magellan, 0-in Design Automation, Verix ,References,Assertion-based coverage metrics revolutionize verification By Curt Widdoes, EEdesign Understanding Assertion-Based Verification By Richard G. Stolzman System-on-a-chip Verification Methodology and Techniques By Prakash Rashinkar, Peter Paterson, Leena Singh Co-Verification from Hardware and Software from ARM SOC Design Leveraging Assersion Based Verification Using Magellan By Jacob Anderson, Peter Jensen, SNUG Boston 2005,Thank you,Q & A,
