1、Mix-signal MOS Design,Coming Chen,High Speed,Gain Stage,Dynamic Range,Matching,FET & LPNP matching,Cap matching,Resistor matching,Thermal noise or NF & 1/f noise,Linearity Harmonic Distortion,Advanced CMOS Analog Design,V/L BJT,Mixed Signal Technology Concern,Device Characteristics for Analog/RF,Ana
2、log: High Gm/ID ratio for Lower power But, CMOS has lower ratio. High Early Voltage (VA) for higher gain Deep submicron CMOS suffers lower VA. Good Linearity and low noise: Dynamic range and signal purity CMOS is good. Good matching: CMOS has VT and area mismatch issues (BJT is better). Low temperat
3、ure linearity: BJT is needed for zero-temperature bias circuitry. RF: Low Noise Figure and : Dynamic range and signal purity in radio frequency. CMOS has higher NF (GaAs has better NF) and Low 1/f noise: important for narrow band application. CMOS has worse 1/f noise among different device technolog
4、ies. Low Gate/base resistance: In deep sub-micron CMOS, gate resistance limited the width of transistor. Together with edge parasitics concern, combination of device width and total fingers has to consider all the different specification. Low Power: Good Substrate Isolation: Crosstalk suppression an
5、d high-Q on-chip components III-V and SOS CMOS can provide insulating substrate. Deep N-well.,Requirements for Analog MM/RF,3.3V FET are more widely used than core devices. Gm/ID ratio and Gm: Drivability. VA early voltage: Transistor Intrinsic Gain lower power consumption. Cgg and Junction Cap: Sma
6、ller capacitance results in higher speed and better stability. FET matching: Offset voltage (trade-off with chip area) Need detailed Vgs matching at operation range instead of VT matching Nitrided Gate Oxide (compared to Pure Oxide): It has smaller low-field mobility (mn) smaller mn at lower VGT. Mu
7、ch higher 1/f noise, impacting on voice band, RF band, direct-conversion. Parasitic Bipolar Transistor: b 3, good VBE matching, lower 2kT current. Vertical PNP can be good for PTAT and Bandgap reference. High-performance Lateral PNP Noise Figure (NF),Device Technology Comparison,CMOS:VTH mismatch, h
8、igher 1/f noise, and lower Gm/ID ratio (drivability).Good linearity, low cost, suitable for low voltage application.SOI CMOS:worst VTH mismatch, much higher low-frequency noise. (compared to CMOS): higher wafer cost, and floating body effect.Lower junction capacitance and free of body effect for hig
9、h speed/low power applications.BJT and SiGe HBT in BiCMOS:Expensive process, limited for low voltage application (limited by VBE). Con: Higher Gm/ID ratio, Higher FT and Fmax, especially for SiGe for high speed SONET application. Lower 1/f noise (10 to 100x smaller than CMOS), Good matching property
10、.,Passive Device for Analog MM/RF,Precision Capacitor, 1. 3s Matching, 2. Linearity (VCC), 3. Precision (range), 4. Density (fF/um2). VMIM and MOSCAP and LMIM Cap support. Precision Resistor, 1. 3s Matching, 2. Temperature Coeff. (TCR) and VCR, 3. Precision (range), 4. Sheet Rho (W/1). Unsalicide Po
11、ly resistor and Spice model. On-chip Inductor, 1. Q, density and fSR, 2. 3s Matching (for differential pair loading), 3. Coupling. For high Q, current effort is to reduce Rs. How about substrate loss? special ground plane or low-K! Design Kit: Impact of inductor thickness, metal width and spacing on
12、 Q, density and fSR. Cover from 900MHz to 4GHz. Varactor, 1. Tuning range. 2. Q. 3. Density. N-MOSCAP and P+/N junction Varactors.,Passive device - Resistor,Performance requirements: Sheet Rho and Range. Range can be improved by process optimization. 3s matching. (3s 3000ppm/C). Unsalicide poly P- r
13、esistor can replace it with an extra Mask cost increase and much higher TCR.,Passive Device - Capacitor,Performance requirements: Precision: Capacitance and Range. Density: high density capacitor save chip area. Cap matching and VCC1: Good matching save chip area. Substrate loss and Q: stray capacit
14、ance can increase signal loss. Capacitor Family: Metal-Insulator-Metal Capacitor (VMIM): needs intra-metal layer and one extra mask. Good 3s matching ( 1fF/um2) Free for digital process with lower TCC1 and VCC1 than VMIMs, but mismatch is higher than VMIMs. Q is high due to narrow metal spacing ( 0.
15、3um). Cu backend process is a challenge due to Cu metal profile and CMP issues. MOS Capacitor: for by-pass capacitor or coupling capacitor. Free for digital process with higher density (good for lower frequency by-pass) VCC and breakdown voltage are worst with high stray capacitance. Shared similar
16、Design Kit with N-MOSCAP varactor.,Passive Device- Inductor,Performance requirements: Q: High Q is needed for low noise and high performance. Density: Mismatch: Substrate loss and coupling: Self-resonant frequency, fSR:Inductor Family: Spiral Inductor: Tend to implement in top Two layers to reduce t
17、he substrate loss. But, it doesnt help too much as operating frequency keep increase. Lower resistance (such as using Cu) can increase Q. But, it will be limited by skin effect while Cu thickness keep increase. In current commodity CMOS process, Q can only achieve 10 to 15. Need to evaluate the impr
18、ovement on low-K backend flow. Need to have detailed design kit for the layout matrix with optimized Q, fSR and inductance.,Passive device - Varactor,Performance requirements: Tuning range. Q: Density:Varactor Family: PN Junction Varactor: Operate PN junction diode in reverse bias. Good linearity. B
19、ut, smaller tuning range, lower Q, and smaller capacitance. It needs at least 25% tuning range (0.5V to 2.5V) with shorter Poly length for higher Q. MOSCAP Varactor: Operate a MOS as Capacitor in either depletion or accumulation modes. Larger tuning range, but the slope is sharper which requires mor
20、e careful design in coding. Larger Q and larger capacitance per area.,MM Device Concern - DC Gain,+,-,Q1,Q2,Q4,Q3,i,i,i,Higher AVa. Larger VA,b. smaller Veff=VGS-Vt,I,Why we need better Gm and Rout: Higher Gm can provide either high speed or low power, it can further shrink FET width to have smaller
21、 Cgg to leverage design. Higher Rout can provide larger gain for precision requirement.,Analog Device Parameter Summary,MOS Parameters:OpAmp design: Intrinsic Gain: Lower DC gain is correlated with lower intrinsic gain (gm*Rout), due to worse DIBL in UMC 3.3V NFET design Speed: Lower input stages Gm
22、: Higher surface concentration causes lower mobility (mn.) Worse DIBL causes higher l, resulting in lower Gm. Nitrided oxide has inherent smaller low-field mobility (mn.) Higher parasitic capacitance Cpar: Cgg: dominated by Cox, which is similar in same technology node. CJ (=CJ,Area + CJ,SW): Due to
23、 its heavy pocket imp, UMC has higher CJ,SW.,Issues on 3.3V NFET - II,Vgt = 0.3V,Vgt = 0.2V,Early Breakdown,General behavior of output resistance,Substrate Current Induced Body Effect (SCBE),Drain induced barrier lowering (DIBL),Channel Length modulation,Drain voltage modulation w/ and w/o pocket de
24、sign,Trade off of SCE & VA w/ and w/o Pocket design,MM Device Concern - Matching,Resistor Mis-Match,K value Mis-Match,Vt Mis-Match,Impact of Nitrided Oxide on 1/f noise,10x10 nMOS was used to compare the impact of gate oxide on 1/f noise: Furnace Nitrided process degrade 10dB on core device Smaller
25、degradation was observed on 3.3V FET due to thicker oxide,Gate Oxide Scaling on 1/f Noise,There are two basic 1/f noise mechanisms: Number fluctuation model where Mobility fluctuation model Number fluctuation dominates at low VGT (analog operation range),Background thermal noise is too high,1/Cox2,T
26、ox = 65A (3.3V),32A (1.8V),27A (1.5V),UMC 0.13um 1/f Noise,UMC 0.18 substrate noise- P+ guard ring,UMC 0.18 substrate noise-n-well guard ring,VBJT in CMOS Analog Design,Parasitic BJT is crucial in CMOS Analog design because it can form unique temperature independence bandgap reference: It requires b 3 and good ideality (less 2kT current) in the operating range (0.5V to 0.7V).,PTAT or Bandgap Reference,Gate-Controlled Lateral PNP BJT,Common Base Configuration,VB = 0V, VG = -0.4V 0.4V PMOS off and LPNP onVG 0.4VBelta 100PMOS on and LNPNP offVG 0.6VBelta smaller,
