1、STM8S Standard Peripherals,STM8S Technical Training,May 2008,May 2008,2,Purpose,The purpose of this part is : To present you all the standard peripheral set, containing: GPIO ADC Timers To focus on the new functionalities comparing to ST7,May 2008,3,Objective,At the end of this chapter you will be a
2、ble to Use GPIO, ADC and Timer List all the features of standard peripherals Configure peripherals according to your needs,May 2008,4,STM8S General Purpose I/Os,May 2008,5,GPIO Features (1/2),70 multifunction bi-directional I/O ports for the 80 pin package Up to 70 Standard I/Os (3mA drive and 8mA f
3、or High-sink capable I/Os) Up to 16 analog inputs Up to 38 I/Os can be set-up as external interrupts including TLI (with sensitivity selection) Up to 37 with wake-up capability All Standard I/Os are shared in 9 ports (GPIOAGPIOI) Individually configurable (Direction, configuration, ext. int., slope
4、) Separate registers for data input and output Allowing bit handling on the GPIO register,May 2008,6,GPIO Features (2/2),Highly robust I/O design, immune against current injection some I/Os with 10 MHz toggling frequency capabilitywith output slope control for EMC noise reduction Alternate Functions
5、 pins (like USARTx, TIMx, I2Cx, SPIx, CAN, ),May 2008,7,GPIO Configuration Modes,Bit Set/Reset Registers,Input Data Register,Output Data Register,Read / Write,I/O pin,Analog Input,Alternate Function Output,To On-chip Peripherals,From On-chip Peripherals,TTL Schmitt Trigger关掉,OUTPUT CONTROL,ON,VDD_IO
6、,VSS,OFF,Input Driver,Output Driver,Read,Write,Disabled,May 2008,8,GPIO Configuration Modes,Bit Set/Reset Registers,Input Data Register,Output Data Register,Read / Write,I/O pin,Analog Input,Alternate Function Output,To On-chip Peripherals,From On-chip Peripherals,Push-Pull Open Drain,TTL Schmitt Tr
7、igger,OUTPUT CONTROL,ON,VDD_IO,VSS,OFF,0,Input Driver,Output Driver,Read,Write,Disabled,NEW,NEW,X,X,Only on I2C I/Os,X,Pin value is readable,May 2008,9,Programming Tips for GPIOs (1),A/D conversion Each pin used by the ADC cell must be configured as floating input (i.e. without pull-up resistors) be
8、fore activating the analog input mode (which is the usual default state) Alternate function A signal coming from an on-chip peripheral can be output on a port. In this case, the I/O is automatically configured in output mode through Px_DDR A signal coming from an I/O can be an input to an on-chip pe
9、ripheral. In this case, it must be configured according to the peripheral. WARNING Peripherals do not modify the complete I/O configuration: Px_CR1 registers are not forced by hardwareYOU NEED TO MANAGE Px_CR1 BY SOFTWARE,May 2008,10,Programming Tips for GPIOs (2),Open Drain Outputs can be used for
10、bus driving where several devices are connected on the same line (to avoid conflicts: lines can be pulled low or in high impedance) . I/Os can be wired together in parallel to increase current drive capabilityVoltages driving an Analog Input should always stay within the absolute maximum ratings (Vs
11、s-0.3V to Vdd+0.3V) Pull-up resistors typically deliver (tbc)A under 5V,May 2008,11,Quiz,What is the equivalent name of the ST7 option register (OR)? Px_CR1 ( Control register 1). How to enable the external interrupt on STM8 ? By setting CR2 bit when GPIO is configured a input thanks to DDR (bit cle
12、ared). What is the use of limiting the transition slope when GPIO is configured in output ? To reduce the EMC noise to improve Electro-Magnetic Compliance. Which instruction can be now used on Px_ODR and should not be used on ST7 DR register ? BSET and BRES can now be used thank to the new Read-Writ
13、e-Modify functionality and the new Px_IDR.,May 2008,12,STM8S ADC,May 2008,13,ADC Features,10 bit ADC16 multiplexed input channels Conversion time 3.5 s min ADC clock range: 1 to 4 MHzInput range Vref- Vin Vref+Vref- range 0 to 0.5V; Vref+ range 2.75 to VddaExternal trigger and timer trigger selectio
14、nSingle or continuous conversion modesAuto power-down in single modeEnd of conversion interruptData alignment Clock prescaling,May 2008,14,Block Diagram,ANALOG TO DIGITAL CONVERTER,Power/ Analog pins,Clock Prescaler,Data Register 10 bits,VREF+ VREF- VDDA VSSAAIN00 AIN01 . . .AIN15PD4,GPIOs,Timer 1,f
15、ADC,fMASTER,ADC Registers,EOC End of Conversion,Interrupt,Trigger,Data bus,May 2008,15,Conversion Modes,SingleContinuous,May 2008,16,D1 D0,D9 D8,Clock Setting and Data Alignement,Clock prescalerData Alignment,Clock Prescaler,fMASTER,fADC,SPSEL2:0 Speed select,D1 D0,D9 D8,LEFT Alignment,RIGHT Alignme
16、nt,ADC_DRH,ADC_DRL,ADC_DRH,ADC_DRL,May 2008,17,Channel Selection Conversion on External Trigger Schmitt Trigger Selection,Timer 1,Trigger,Trigger select,AIN00 AIN01 . . . AIN15PD4,GPIOs,Analog input,May 2008,18,Analog zooming,Vref-,Vref+,VDDA,VSSA,Min = 0V, Max = 0.5V,Min = 2.25V Max = 5.5V,Min = 0V
17、, Max = 2.75V,May 2008,19,Quiz,What is the max clock frequency for ADC and what is the conversion time for maximum ADC clock? ADC clock freq. max = 4 MHz Conversion time = 3.5 s How can you trigger an analog conversion ? By setting ADON (if the ADC is not in power down mode) By external triggering (
18、Timer or ADC trigger) By selecting another channel if a conversion is on going How should be configured the I/O which is used as ADC input channel? Input floating (schmitt trigger is automatically disabled during conversion but for lower power consumption it is advise to statically disable the schmi
19、tt trigger thanks to ADC_TDRx),May 2008,20,STM8S TIMER PERIPHERALS,May 2008,21,STM8S Timers,The STM8S device embeds 4 timer Timer 1 16 bit, 4 channels, Motor Control timer Timer 2,3 16 bit, 3,2 channels, General Purpose timers Timer 4 8 bit, 0 channels, System timer,May 2008,22,STM8S Timer 1 Feature
20、s,16-bit Counter Up, down and centered (up&down) counting modes Auto Reload Programmable prescaler Repetition counter 4 x 16 bit Channels Input Capture, PWM Input Capture Output Compare, PWM outputs (edge or center-aligned) One pulse mode output Complementary outputs & Dead time, Forced output mode
21、Encoder interface, Hall Sensors interface (MC) Synchronization Reset, Triggered or Gated modes Break input Interrupts & Update Event Counter overflow / underflow Counter initialization Trigger, Break, Commutation Input capture, Output compare,May 2008,23,Time Base Unit,General Block Diagram,Clock/Tr
22、igger Controller,Trigger output,Clocks,16-Bit up-down Counter,Output Compare Input Capture Register,TI1,TI2,TI3,Triggers,TI4,Input Stage,Input Stage,Input Stage,Input Stage,Input Stage,Input Stage,Input Stage,Output Stage,OC1/1N,OC2/2N,OC3/3N,OC4,Capture Compare Array,Auto Reload Register,Repetition
23、 Counter,Prescaler,Break,May 2008,24,Block Diagram Details,Clock/Trigger Controller,Time Base Unit,Capture/Compare Array,Input Stage,Output Stage,Capture Compare Stage,May 2008,25,Time Base Unit: Block diagram,Notes UEV - Update Event OPM - One Pulse Mode CEN - Counter Enable UG - Update Generation
24、UDIS Update Disable ARPE Autoreload Preload Enable DIR - Direction,May 2008,26,Time Base Unit: Update Event (UEV),The Update Event is used to trigger the transfer from the preload registers to shadow registersRegisters with shadow: Prescaler Auto Reload Capture Compare (in Capture Compare Array) Rep
25、etition Counter Update Event is generated: on overflow or underflow event when the counter is reinitialized by software by a trigger event,May 2008,27,Update Event,Timer Clock,Auto Reload,Time Base Unit: Counter Modes,Update Event,Timer Clock,Auto Reload,Update Event,Up counting mode,Down counting m
26、ode,Center-aligned mode,EDGE-ALIGNED,CENTER-ALIGNED,May 2008,28,Clock Controller,Clock selection Internal clock (fMASTER) External Timer Input pins, 1 & 2 External Timer Trigger input pinClock Trigger Modes: Trigger Gated ResetNotes UEV - Update Event OPM - One Pulse Mode CEN - Counter Enable UG - U
27、pdate Generation,May 2008,29,Trigger Controller,Trigger Input ETR TI1 TI2 Trigger Output (ADC) Update Generation Counter Enable Update Event Compare Pulse,May 2008,30,Capture/Compare Array: Register Stage,Notes UEV - Update Event CC1E Capture Enable CC1G Capture Generation OC1PE Preload Enable CCRx
28、Capture/Compare Register,May 2008,31,Capture/Compare Array: Input Stage,Filtering Edge Detection Trigger selection Capture Selection Dividing,CC1P _,May 2008,32,Input capture registers are used to latch the value of the counter after a transition detected by the corresponding Input Capture pin.,Inpu
29、t Capture Mode,Configure: Source Filter duration Polarity selection Edge Detection Divider,Polarity Select & Edge Controller & Divider,Capture Register,Counter,May 2008,33,PWM Input Mode,Enables the measurement of the period and the pulse width,Timer Clock,IC1 - DUTY CYCLE,IC2 - PERIOD,Counter,Exter
30、nal PWM,6,10,Rising edge: resets the counter and capture periodFalling edge: capture duty cycle,May 2008,34,Capture/Compare Array: Output Stage,Output Compare Clear Output Compare Mode Dead Time Polarity Output State and Enable Selection,May 2008,35,Output Compare Mode,Set Reset Toggle Remain unchan
31、gedGenerates an interruptOutput Compare register update can be configured as: Immediate On update event (Auto-reload update),Timer Clock,CCR1,Interrupt,New CCR1,CC1,Interrupt,Used to control an output waveform or indicate when a period of time has elapsed.When a match is found between the Compare re
32、gister and the counter, the output pin can be programmed as:,May 2008,36,PWM Modes,Generate independent signals with programmable frequency and a duty cycleAuto-reload register (ARR) define the PWM period in Edge-Aligned mode Half PWM period in Center-Aligned mode Each PWM channel has a capture comp
33、are register (CCR) to define the duty cycle,CCR,0,UDF,OVF,OVF,ARR,0,0,0,OVF,UDF,UDF,OVF,OVF,UDF,OVF,ARR,CCR,ARR,CCR,Edge-Aligned Up counting mode,Edge-Aligned Down counting mode,Center-aligned mode,May 2008,37,One Pulse Mode,Delay defined by Output Compare register value Length defined by the differ
34、ence between Auto Reload register value and Compare valueThere are two One Pulse Modes Single Pulse Repetitive Pulse - defined by repetition counter,TIM_ARR,TIM_CCR1,t,TI1 input,TIMx_CH1 output,DELAY,LENGTH,Generate a pulse with a programmable length after a programmable delay as response to a stimu
35、lus,May 2008,38,Break Function,When a break occurs Main Output Enable is cleared - outputs are put to programmable save state even MCU oscillator is off The break status flag is set and an interrupt can be generatedThe break is generated by Hardware - input which has a programmable polarityAutomatic
36、 Output Enable If the Automatic Output Enable (AOE) is set, the MOE bit is automatically set again at the next update event UEVThis can be used to perform a regulation. If the AOE is Reset, the MOE remains low until you write it to 1 againIt can be used for security. The break input can be connected
37、 to an alarm from power drivers, thermal sensors or any security components.Break Safeguard Circuit Write protection to freeze break configuration 3 levels of protection,May 2008,39,Complementary outputs & Dead time Insertion,This mode allows Outputs two complementary signals for each three channels
38、. Polarity can be selected independently Manage the dead-time between the switching-off and the switching-on instants of the outputs.Reference waveform OCxREF generates 2 outputs OCx and OCxN for the three channels. OCx rising edge is delayed to reference rising edge OCNx rising edge is delayed to r
39、eference falling edge,OCxREF,OCx,OCxN,t,delay,delay,May 2008,40,Output Control with Break,May 2008,41,Encoder Interface,The two inputs TI1 and TI2 are used to interface to an incremental encoder without external interface logic. The sequence of transitions of the two inputs is evaluated and generate
40、s count pulses as well as the direction signal by hardware accordingly. The counter provides information on the current position and DIR control bit provides information on the encoder direction.The encoder output which indicates the mechanical zero position, may be connected to an external interrup
41、t and can trig a counter reset.,Trigger Controller,Controller,Encoder Interface,Polarity Select & Edge Controller,Polarity Select & Edge Controller,TI2,CLK_PSC,May 2008,42,Hall sensors Interface 1/2,How to configure the TIM to interface with a Hall sensor Select the hall inputs: TI1 is XOR combinati
42、on of CC1, CC2 and CC3 The trigger controller configure in reset mode. TI1 is trigger signal (each time one of the 3 inputs toggles the counter restart from zero) Channel 1 configure in capture mode (this value correspond to the time between 2 changes on the inputs = it gives the motor speed),May 20
43、08,43,Prescaler,Input Filter & Edge detector,TRC,Prescaler,Capture/Compare 2 Register,Input Filter & Edge detector,Capture/Compare 3 Register,Input Filter & Edge detector,TRC,TRC,Prescaler,IC2,IC3,IC4,Capture/Compare 4 Register,TRC,Hall sensors Interface 2/2,XOR,Input Filter & Edge detector,Capture/
44、Compare 1 Register,Prescaler,TI4,IC1,Hall A,Hall B,Hall C,TI1F_ED,Clock/TriggerController,May 2008,44,STM8S Timer 2,3 Features,16-bit Counter Up counting modes Auto Reload Programmable prescaler 2-3 x 16 bit Channel Input Capture Output Compare PWM (edge -aligned) One pulse mode output Forced output
45、 mode Interrupts & Update Event Counter initialization Input capture, Output compare,OC1,Prescaler,Internal Clock,Auto Reload Register,16-Bit up Counter,Output Compare Input Capture,TI1,TI2,TI3,OC2,OC3,May 2008,45,STM8S Timer 4 Features,8-bit Counter Up counting mode Auto Reload Programmable prescal
46、erUpdate Event & Interrupts Counter initialization,Prescaler,Internal Clock,Auto Reload Register,8-Bit up Counter,May 2008,46,Quiz,Up to how many TIM timers are available in the STM8 device? 3 x 16-bit timers, TIM1, TIM2 and TIM3 + 1 x 8-bit timer, TIM4.How many pins on the product are implemented p
47、er channel? One pin only: IC and OC are mapped on the same pin. This is different compared to ST7 and it is potentially an issueWhat are the main counter clock sources? 3 main sources: Internal clock (fMASTER), External input pins 1 or 2, External Trigger pin (TIM1_TRIG)What can I measure with PWM input mode? I can measure the period and duty cycle of an input signal,
