1、锁相技术译文翻译英文原文：An On-Chip All-Digital Measurement Circuit to Characterize Phase-Locked Loop Response in 45-nm SOI译文： 45纳米 SOI全数字片上测量电路表征锁相环响应特性年级专业： 姓名： 学号： 2013 年 6 月 2 日第 2 页/ 共 6 页英文 中文An On-Chip All-Digital Measurement Circuit to Characterize Phase-Locked Loop Response in 45-nm SOI AbstractAn all-
2、digital measurementCircuit , built in 45-nm SOI-CMOS enables on-chip characterization of phase-locked loop (PLL) response to a self-induced phase step. This technique allows estimation of PLL closed-loop bandwidth and jitter peaking. The circuit can be used to plot step-response vs.time, measure sta
3、tic phaseerror, and observe phase-lock status. INTRODUCTION Many applications such as PCI Expressrequire a PLL to produce alow-jitter clock at a given frequency while meeting stringent bandwidth and jitter peaking requirements. Process, voltage, and temperature (PVT) variations as well as random dev
4、ice mismatch makeit difficult to guarantee a narrow range for PLL response. For example ,loop parameters such as VCO gain could vary by more than 2X over PVT corners. In Fig. 1, we see the closed-loop jitter transfer functions of two PLLs with identical reference clock and output frequencies. One PL
5、L exhibits large peaking and low bandwidth while the other shows little peaking but high bandwidth. Although differences in this example are more extreme than usual, similar but smaller differences often result from PVT variations. 45纳米 SOI全数字片上测量电路表征锁相环响应特性摘要-建立在 45纳米的 SOI-CMOS上一个全数字测量电路，它能够表征 PLL对
6、自诱导相步进的响应这项技术允许对 PLL闭环带宽和抖动峰值的估计。这个电路被用来绘制阶跃响应随时间变化的曲线，测量静态相位误差和观察相位锁定状态。介绍很多应用例如 PCI Express需要一个 PLL来产生一个低抖动的在一个给定频率的时钟，这个频率满足精确带宽和抖动峰值的要求。工艺，电压，和温度（PVT）变化以及随机的选择不搭配的器件都使得很难保证一个窄的变化范围的 PLL响应，例如，环路参数如 VCO增益变化可能超过 PVT角 2倍上以。图一中，我们可以看到两个具有相同参考时钟和输出频率 PLL的闭环抖动传递函数一个 PLL展现大的峰值和低带宽，而另一个展示了小峰值但是高带宽虽然这个例子中
7、显示的差异比通常的要极端，这种相似会随着 PVT的变化而变小PLL的响应往往使用一个信号发生器、示波第 3 页/ 共 6 页PLL response is often measured on atest bench using signal generators, oscilloscopes, and/or spectrum analyzers. For example, the transfer functions in Fig. 1 were automatically generated by modulating the 100-MHz reference clock with var
8、ious frequencies while observing the amplitudes of the resulting output spurs. Such methods, which may require many seconds to complete, motivate the need for faster, less expensive, and preferably on-chip techniques to characterize PLL response 1-3. Fig. 2 shows the PLL output phase transient respo
9、nse to an induced phase step. Similar to other second-order feedback systems, the PLL tends to overcorrect (or overshoot) as it works to eliminate the induced phase error. If the PLL is underdamped, as in this example, the PLL may ring several times before settlingto its final lockstate. A key metri
10、c in the PLL step-response is crossover, defined here asthe elapsed time from input step toonset of phase overshoot. Another key metric is MaxOvershoot. It measures the maximum overcorrectionin the step response. Transient simulations and closed-form loop equations 4 show that crossover is inversely
11、 proportional to thePLLs 3dB closed-loop bandwidth; the smaller crossoveris, the higher the bandwidth (Fig. 3). Notice that crossover is largely independent of the size ofthe phase step. Both simulations and loop equations also predict that MaxOvershoot is proportional to the maximum peaking in the
12、closed-器，和/或频谱分析仪。例如，在图一中传递函数是通过调制 100MHz能产生各种频率的参考时钟同时观察输出马刺产生的幅值自动生成的。这种方法，可能需要一些时间去完成，这促进了更快，更便宜的方法的需要。比较好的方法是片上系统来表征 PLL的响应特性1-3。表二表明致相步进响应的输出瞬态相位。类似于其他二阶反馈系统，PLL 倾向于过调（或过调） ，那是因为它是为了消除相位误差。如果锁相环工作在欠阻尼状态，在这种状态下，PLL 可能要经过几次锁存在达到最终锁存状态之前锁相环阶跃响应的一个关键指标是交叉反应。在此定义为从输入步进到相位超调开始出现所用的时间另一个关键指标是最大超调量。它可以
13、测量阶跃响应的最大过调量。瞬态模拟和闭环回路方程4表明交叉反应和 PLL的 3dB闭环带宽成反比；交叉反应越小，带宽越大（图 3） 。请注意，交叉反应在很大程度上与相位步长无关。模拟和回路方程还预测到闭环传递函数中最大超调与最大峰值是成正比的;第 4 页/ 共 6 页loop transfer function; the larger MaxOvershoot is, the greater the peaking (Fig. 4). Notice thatthe magnitude of the overshoot isalso proportional to theinput stepsi
14、ze .These relationships between time-and frequency-domain behaviors allow us to make fasttime-domain measurements and then relate the results back to frequency-domain performance specifications. The circuit implementation presented in this papershows that the PLL step response may be captured by ana
15、ll-digital, on-chip finite statemachine, allowing forfast PLL characterization. Silicon results indicate that this circuit couldallow for Power-on calibration of the PLL bandwidth and peaking for compensation of process variations.CIRCUIT DESIGN The PLL under test (Fig. 5) isa standard integer-N cha
16、rge-pump PLL. The only modification is the addition of loop measurement circuitry. The feedback divisor (N) isprogrammable from 5 to 63 ，although N=8 during loop measurement tests. The charge-pump current, loop-filter resistance, and VCO gain are programmable to allow for bandwidth and peaking adjus
17、tments aswell as jitter optimization. The PLL bandwidth may be configured from 3 to 25 MHz while the peaking may be varied from 4dB. The VCO operates from 1.6 to 5 GHz. The expected reference clock frequency range is 100 to 200 MHz.A simple way to induce the required input phase step is to flip the
18、polarity of the reference clock so 最大超调越大，峰值越高（图 4） 。请注意超调幅度也正比于输入步长。时域和频域的这种特性使得我们能够快速的时域测量然后关联到频域性能指标中去，电路实现显示：PLL阶跃响应可能被全数字化片上有限状态机捕获，从而实现快速表征锁相硅的实验效果表明，该电路可以让 PLL带宽和峰值的电校准工艺变化得到弥补。电路设计 被测 PLL（图 5）是一个标准的整数 N电荷泵锁相环。唯一的修改就是增加了回路测量电路。反馈除数（N）是由 5至 63可编程的，虽然在回路测量试验中 N=8。电荷泵电流、循环过滤电阻和 VCO增益可编程，以允许带宽和峰值
19、的调整以及抖动的优化。 PLL带宽可配置为 3到 25MHz，而峰值可在1至 4 分贝之间变化。VCO操作频率范围为 1.6到 5GHz。预期的参考时钟频率范围为 100至 20MHz一个简单的诱发所需输入相位的方法是翻转极性参考时钟使其相位提前半个时钟周期。第 5 页/ 共 6 页its phase is advancedby half a clock cycle. A disadvantage to this approachis that the magnitude of the phase step is dependent on the reference clock duty cy
20、cle. This is undesirable because overshoot tests require a large and predictable input phase step. Instead, the circuit implementation presented here manipulates the feedback divisor to induce a known phase step. The circuit then automatically measures the resulting crossover and MaxOvershoot. Fig.6
21、 shows a block diagram of the loop measurement test circuit. It includes three main units: control,crossover detector, and MaxOvershoot detector. The control unit contains two synchronizers (to VCO clock), threeedge detectors (rising and falling), andlogic to enable the induced phase step. The cross
22、over detector includes a bang-bang phase detector, a phase-error change-of-sign detector, and a 10-bit counter. The MaxOvershoot detectorcontains a feedback count sampler, a comparator, and a maximum overshoot register. These step-response algorithms require that the PLL static phase error is less t
23、han themaximum overshoot. If not true, therequired phase error sign-change does not occur, the bandwidth counter saturates at its maximum value,and the BwValid bit remains low. If the static phase error is large, then the FbClk phase can beadvanced, forcing a phase error sign-change. The resolution
24、of the bandwidth test is one reference clock 这种方法的一个缺点是，相步距大小与参考时钟占空比有关。这是不可取的，因为超调测试需要一个大且可预见输入相位步进。相反，这里呈现的电路通过操作诱导反馈除数来诱导已知相位步进。该电路将自动测试产生的交叉反应和最大超调量。图 6显示了一个环路测量测试电路的框图。它包括三个主要单元：控制模块、交叉反应检测器，和最大超调探测器。控制单元包含两个（对 VCO时钟的）同步器，三个（上升和下降）边沿探测器，和使能致相一步的逻辑。交叉反应检测器包括一个快速相器检测器，一个相位误差符号变化探测器和一个 10位计数器。该最大超
25、调探测器包含一个反馈计数采样器，一个比较器，和一个最大超调寄存器。这些步进响应算法要求 PLL静态相位误差小于最大超调量。如果不是这样的话，需要的相位误差符号变化不会出现，带宽计数器达到最大值而饱和，而 BwValid位仍然为低。如果静态相位误差较大，则 FbClk相位可能被提前，迫使相位误差符号变化。第 6 页/ 共 6 页period, and so the measurement becomesless precise as the PLL bandwidth Approaches the reference clock frequency.带宽测试的解决方法是一个参考时钟周期，因此测量因 PLL带宽接近参考时钟频率而变得不那么精确
