1、SOLOMON SYSTECH SEMICONDUCTOR TECHNICAL DATA This document contains information on a new product. Specifications and information herein are subject to change without notice. http:/www.solomon- SSD1306 Rev 1.0 P 1/59 Sep 2007 Copyright 2007 Solomon Systech Limited Advance Information SSD1306 128 x 64
2、 Dot Matrix OLED/PLED Segment/Common Driver with Controller Solomon Systech Sep 2007 P 2/59 Rev 1.0 SSD1306 CONTENTS 1 GENERAL DESCRIPTION .6 2 FEATURES.6 3 ORDERING INFORMATION .6 4 BLOCK DIAGRAM 7 5 DIE PAD FLOOR PLAN 8 6 PIN ARRANGEMENT11 6.1 SSD1306TR1 PIN ASSIGNMENT 11 7 PIN DESCRIPTION 13 8 FU
3、NCTIONAL BLOCK DESCRIPTIONS.15 8.1 MCU INTERFACE SELECTION 15 8.1.1 MCU Parallel 6800-series Interface 15 8.1.2 MCU Parallel 8080-series Interface 16 8.1.3 MCU Serial Interface (4-wire SPI) 17 8.1.4 MCU Serial Interface (3-wire SPI) 18 8.1.5 MCU I2C Interface. 19 8.2 COMMAND DECODER . 22 8.3 OSCILLA
4、TOR CIRCUIT AND DISPLAY TIME GENERATOR. 22 8.4 FR SYNCHRONIZATION . 23 8.5 RESET CIRCUIT. 23 8.6 SEGMENT DRIVERS / COMMON DRIVERS 24 8.7 GRAPHIC DISPLAY DATA RAM (GDDRAM). 25 8.8 SEG/COM DRIVING BLOCK . 26 8.9 POWER ON AND OFF SEQUENCE 27 9 COMMAND TABLE .28 9.1 DATA READ / WRITE 33 10 COMMAND DESCR
5、IPTIONS .34 10.1 FUNDAMENTAL COMMAND 34 10.1.1 Set Lower Column Start Address for Page Addressing Mode (00h0Fh) . 34 10.1.2 Set Higher Column Start Address for Page Addressing Mode (10h1Fh) 34 10.1.3 Set Memory Addressing Mode (20h) 34 10.1.4 Set Column Address (21h) . 35 10.1.5 Set Page Address (22
6、h) 36 10.1.6 Set Display Start Line (40h7Fh) 36 10.1.7 Set Contrast Control for BANK0 (81h) 36 10.1.8 Set Segment Re-map (A0h/A1h) . 36 10.1.9 Entire Display ON (A4h/A5h) 37 10.1.10 Set Normal/Inverse Display (A6h/A7h) 37 10.1.11 Set Multiplex Ratio (A8h). 37 10.1.12 Set Display ON/OFF (AEh/AFh) . 3
7、7 10.1.13 Set Page Start Address for Page Addressing Mode (B0hB7h). 37 10.1.14 Set COM Output Scan Direction (C0h/C8h) 37 10.1.15 Set Display Offset (D3h) 37 10.1.16 Set Display Clock Divide Ratio/ Oscillator Frequency (D5h) . 40 10.1.17 Set Pre-charge Period (D9h) . 40 10.1.18 Set COM Pins Hardware
8、 Configuration (DAh). 40 10.1.19 Set VCOMHDeselect Level (DBh) . 43 SSD1306 Rev 1.0 P 3/59 Sep 2007 Solomon Systech10.1.20 NOP (E3h) . 43 10.1.21 Status register Read . 43 10.2 GRAPHIC ACCELERATION COMMAND. 44 10.2.1 Horizontal Scroll Setup (26h/27h) . 44 10.2.2 Continuous Vertical and Horizontal Sc
9、roll Setup (29h/2Ah). 45 10.2.3 Deactivate Scroll (2Eh) 46 10.2.4 Activate Scroll (2Fh) 46 10.2.5 Set Vertical Scroll Area(A3h) 46 11 MAXIMUM RATINGS47 12 DC CHARACTERISTICS.48 13 AC CHARACTERISTICS.49 14 APPLICATION EXAMPLE55 15 PACKAGE INFORMATION56 15.1 SSD1306TR1 DETAIL DIMENSION. 56 15.2 SSD130
10、6Z DIE TRAY INFORMATION 58 Solomon Systech Sep 2007 P 4/59 Rev 1.0 SSD1306 TABLES TABLE 5-1 : SSD1306Z BUMP DIE PAD COORDINATES 10 TABLE 6-1 : SSD1306TR1 PIN ASSIGNMENT TABLE 12 TABLE 7-1 : MCU BUS INTERFACE PIN SELECTION 14 TABLE 8-1 : MCU INTERFACE ASSIGNMENT UNDER DIFFERENT BUS INTERFACE MODE 15
11、TABLE 8-2 : CONTROL PINS OF 6800 INTERFACE. 15 TABLE 8-3 : CONTROL PINS OF 8080 INTERFACE. 17 TABLE 8-4 : CONTROL PINS OF 4-WIRE SERIAL INTERFACE. 17 TABLE 8-5 : CONTROL PINS OF 3-WIRE SERIAL INTERFACE. 18 TABLE 9-1: COMMAND TABLE . 28 TABLE 9-2 : READ COMMAND TABLE. 33 TABLE 9-3 : ADDRESS INCREMENT
12、 TABLE (AUTOMATIC) . 33 TABLE 10-1 : EXAMPLE OF SET DISPLAY OFFSET AND DISPLAY START LINE WITH NO REMAP 38 TABLE 10-2 :EXAMPLE OF SET DISPLAY OFFSET AND DISPLAY START LINE WITH REMAP 39 TABLE 10-3 : COM PINS HARDWARE CONFIGURATION . 40 TABLE 11-1 : MAXIMUM RATINGS (VOLTAGE REFERENCED TO VSS) 47 TABL
13、E 12-1 : DC CHARACTERISTICS 48 TABLE 13-1 : AC CHARACTERISTICS 49 TABLE 13-2 : 6800-SERIES MCU PARALLEL INTERFACE TIMING CHARACTERISTICS. 50 TABLE 13-3 : 8080-SERIES MCU PARALLEL INTERFACE TIMING CHARACTERISTICS. 51 TABLE 13-4 : 4-WIRE SERIAL INTERFACE TIMING CHARACTERISTICS 52 TABLE 13-5 : 3-WIRE S
14、ERIAL INTERFACE TIMING CHARACTERISTICS 53 TABLE 13-6 :I2C INTERFACE TIMING CHARACTERISTICS 54 SSD1306 Rev 1.0 P 5/59 Sep 2007 Solomon SystechFIGURES FIGURE 4-1 SSD1306 BLOCK DIAGRAM 7 FIGURE 5-1 : SSD1306Z DIE DRAWING . 8 FIGURE 5-2 : SSD1306Z ALIGNMENT MARK DIMENSIONS 9 FIGURE 6-1 : SSD1306TR1 PIN
15、ASSIGNMENT . 11 FIGURE 7-1 PIN DESCRIPTION. 13 FIGURE 8-1 : DATA READ BACK PROCEDURE - INSERTION OF DUMMY READ . 16 FIGURE 8-2 : EXAMPLE OF WRITE PROCEDURE IN 8080 PARALLEL INTERFACE MODE. 16 FIGURE 8-3 : EXAMPLE OF READ PROCEDURE IN 8080 PARALLEL INTERFACE MODE 16 FIGURE 8-4 : DISPLAY DATA READ BAC
16、K PROCEDURE - INSERTION OF DUMMY READ. 17 FIGURE 8-5 : WRITE PROCEDURE IN 4-WIRE SERIAL INTERFACE MODE. 18 FIGURE 8-6 : WRITE PROCEDURE IN 3-WIRE SERIAL INTERFACE MODE. 18 FIGURE 8-7 : I2C-BUS DATA FORMAT 20 FIGURE 8-8 : DEFINITION OF THE START AND STOP CONDITION . 21 FIGURE 8-9 : DEFINITION OF THE
17、ACKNOWLEDGEMENT CONDITION . 21 FIGURE 8-10 : DEFINITION OF THE DATA TRANSFER CONDITION . 21 FIGURE 8-11 : OSCILLATOR CIRCUIT AND DISPLAY TIME GENERATOR 22 FIGURE 8-12 : SEGMENT OUTPUT WAVEFORM IN THREE PHASES . 24 FIGURE 8-13 : GDDRAM PAGES STRUCTURE OF SSD1306 25 FIGURE 8-14 : ENLARGEMENT OF GDDRAM
18、 (NO ROW RE-MAPPING AND COLUMN-REMAPPING) 25 FIGURE 8-15 : IREFCURRENT SETTING BY RESISTOR VALUE . 26 FIGURE 8-16 : THE POWER ON SEQUENCE 27 FIGURE 8-17 : THE POWER OFF SEQUENCE 27 FIGURE 10-1 : ADDRESS POINTER MOVEMENT OF PAGE ADDRESSING MODE . 34 FIGURE 10-2 : EXAMPLE OF GDDRAM ACCESS POINTER SETT
19、ING IN PAGE ADDRESSING MODE (NO ROW AND COLUMN-REMAPPING) . 34 FIGURE 10-3 : ADDRESS POINTER MOVEMENT OF HORIZONTAL ADDRESSING MODE . 35 FIGURE 10-4 : ADDRESS POINTER MOVEMENT OF VERTICAL ADDRESSING MODE 35 FIGURE 10-5 : EXAMPLE OF COLUMN AND ROW ADDRESS POINTER MOVEMENT 36 FIGURE 10-6 :TRANSITION B
20、ETWEEN DIFFERENT MODES 37 FIGURE 10-7 : HORIZONTAL SCROLL EXAMPLE: SCROLL RIGHT BY 1 COLUMN. 44 FIGURE 10-8 : HORIZONTAL SCROLL EXAMPLE: SCROLL LEFT BY 1 COLUMN . 44 FIGURE 10-9 : HORIZONTAL SCROLLING SETUP EXAMPLE. 44 FIGURE 10-10 : CONTINUOUS VERTICAL AND HORIZONTAL SCROLLING SETUP EXAMPLE 45 FIGU
21、RE 13-1 : 6800-SERIES MCU PARALLEL INTERFACE CHARACTERISTICS 50 FIGURE 13-2 : 8080-SERIES PARALLEL INTERFACE CHARACTERISTICS 51 FIGURE 13-3 : 4-WIRE SERIAL INTERFACE CHARACTERISTICS. 52 FIGURE 13-4 : 3-WIRE SERIAL INTERFACE CHARACTERISTICS. 53 FIGURE 13-5 : I2C INTERFACE TIMING CHARACTERISTICS 54 FI
22、GURE 14-1 : APPLICATION EXAMPLE OF SSD1306Z . 55 FIGURE 15-1 SSD1306TR1 DETAIL DIMENSION 56 FIGURE 15-2 : SSD1306Z DIE TRAY INFORMATION 58 Solomon Systech Sep 2007 P 6/59 Rev 1.0 SSD1306 1 GENERAL DESCRIPTION SSD1306 is a single-chip CMOS OLED/PLED driver with controller for organic / polymer light
23、emitting diode dot-matrix graphic display system. It consists of 128 segments and 64commons. This IC is designed for Common Cathode type OLED panel. The SSD1306 embeds with contrast control, display RAM and oscillator, which reduces the number of external components and power consumption. It has 256
24、-step brightness control. Data/Commands are sent from general MCU through the hardware selectable 6800/8000 series compatible Parallel Interface, I2C interface or Serial Peripheral Interface. It is suitable for many compact portable applications, such as mobile phone sub-display, MP3 player and calc
25、ulator, etc. 2 FEATURES Resolution: 128 x 64 dot matrix panel Power supply o VDD= 1.65V to 3.3V for IC logic o VCC= 7V to 15V for Panel driving For matrix display o OLED driving output voltage, 15V maximum o Segment maximum source current: 100uA o Common maximum sink current: 15mA o 256 step contras
26、t brightness current control Embedded 128 x 64 bit SRAM display buffer Pin selectable MCU Interfaces: o 8-bit 6800/8080-series parallel interface o 3 /4 wire Serial Peripheral Interface o I2C Interface Screen saving continuous scrolling function in both horizontal and vertical direction RAM write sy
27、nchronization signal Programmable Frame Rate and Multiplexing Ratio Row Re-mapping and Column Re-mapping On-Chip Oscillator Chip layout for COG an external clock source must be connected to the CL pin for normal operation. RES# I This pin is reset signal input. When the pin is pulled LOW, initializa
28、tion of the chip is executed. Keep this pin HIGH (i.e. connect to VDD) during normal operation. CS# I This pin is the chip select input. (active LOW) Solomon Systech Sep 2007 P 14/59 Rev 1.0 SSD1306 Pin Name Type Description D/C# I This is Data/Command control pin. When it is pulled HIGH (i.e. conne
29、ct to VDD), the data at D7:0 is treated as data. When it is pulled LOW, the data at D7:0 will be transferred to the command register. In I2C mode, this pin acts as SA0 for slave address selection. When 3-wire serial interface is selected, this pin must be connected to VSS. For detail relationship to
30、 MCU interface signals, please refer to the Timing Characteristics Diagrams: Figure 13-1 to Figure 13-5. E (RD#) I When interfacing to a 6800-series microprocessor, this pin will be used as the Enable (E) signal. Read/write operation is initiated when this pin is pulled HIGH (i.e. connect to VDD) an
31、d the chip is selected. When connecting to an 8080-series microprocessor, this pin receives the Read (RD#) signal. Read operation is initiated when this pin is pulled LOW and the chip is selected. When serial interface is selected, this pin must be connected to VSS. R/W#(WR#) I This is read / write
32、control input pin connecting to the MCU interface. When interfacing to a 6800-series microprocessor, this pin will be used as Read/Write (R/W#) selection input. Read mode will be carried out when this pin is pulled HIGH (i.e. connect to VDD) and write mode when LOW. When 8080 interface mode is selec
33、ted, this pin will be the Write (WR#) input. Data write operation is initiated when this pin is pulled LOW and the chip is selected. When serial interface is selected, this pin must be connected to VSS. D7:0 IO These are 8-bit bi-directional data bus to be connected to the microprocessors data bus.
34、When serial interface mode is selected, D0 will be the serial clock input: SCLK; D1 will be the serial data input: SDIN and D2 should be kept NC. When I2C mode is selected, D2, D1 should be tied together and serve as SDAout, SDAinin application and D0 is the serial clock input, SCL. TR0-TR6 - Testin
35、g reserved pins. It should be kept NC. SEG0 SEG127 O These pins provide Segment switch signals to OLED panel. These pins are VSSstate when display is OFF. COM0 COM63 O These pins provide Common switch signals to OLED panel. They are in high impedance state when display is OFF. NC - This is dummy pin
36、. Do not group or short NC pins together. Table 7-1 : MCU Bus Interface Pin Selection SSD1306 Pin Name I2C Interface 6800-parallel interface (8 bit) 8080-parallel interface (8 bit) 4-wire Serial interface 3-wire Serial interface BS0 0 0 0 0 1 BS1 1 0 1 0 0 BS2 0 1 1 0 0 Note (1)0 is connected to VSS
37、(2)1 is connected to VDDSSD1306 Rev 1.0 P 15/59 Sep 2007 Solomon Systech8 FUNCTIONAL BLOCK DESCRIPTIONS 8.1 MCU Interface selection SSD1306 MCU interface consist of 8 data pins and 5 control pins. The pin assignment at different interface mode is summarized in Table 8-1. Different MCU mode can be se
38、t by hardware selection on BS2:0 pins (please refer to Table 7-1 for BS2:0 setting). Table 8-1 : MCU interface assignment under different bus interface mode Data/Command Interface Control Signal Pin Name Bus Interface D7 D6 D5 D4 D3 D2 D1 D0 E R/W# CS# D/C# RES# 8-bit 8080 D7:0 RD# WR# CS# D/C# RES#
39、 8-bit 6800 D7:0 E R/W# CS# D/C# RES# 3-wire SPI Tie LOW NC SDIN SCLK Tie LOW CS# Tie LOW RES# 4-wire SPI Tie LOW NC SDIN SCLK Tie LOW CS# D/C# RES# I2C Tie LOW SDAOUTSDAINSCL Tie LOW SA0 RES# 8.1.1 MCU Parallel 6800-series Interface The parallel interface consists of 8 bi-directional data pins (D7:
40、0), R/W#, D/C#, E and CS#. A LOW in R/W# indicates WRITE operation and HIGH in R/W# indicates READ operation. A LOW in D/C# indicates COMMAND read/write and HIGH in D/C# indicates DATA read/write. The E input serves as data latch signal while CS# is LOW. Data is latched at the falling edge of E sign
41、al. Table 8-2 : Control pins of 6800 interface Function E R/W# CS# D/C#Write command L L L Read status H L L Write data L L H Read data H L H Note (1) stands for falling edge of signal H stands for HIGH in signal L stands for LOW in signal In order to match the operating frequency of display RAM wit
42、h that of the microprocessor, some pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. This is shown in Figure 8-1. Solomon Systech Sep 2007 P 16/59 Rev 1.0 SSD1306 Figure 8-1 : Data read back procedure - insertion of du
43、mmy read N n n+1 n+2R/W#EDatabusWrite columnaddressRead 1st dataDummy read Read 2nd data Read 3rd data8.1.2 MCU Parallel 8080-series Interface The parallel interface consists of 8 bi-directional data pins (D7:0), RD#, WR#, D/C# and CS#. A LOW in D/C# indicates COMMAND read/write and HIGH in D/C# ind
44、icates DATA read/write. A rising edge of RD# input serves as a data READ latch signal while CS# is kept LOW. A rising edge of WR# input serves as a data/command WRITE latch signal while CS# is kept LOW. Figure 8-2 : Example of Write procedure in 8080 parallel interface mode CS#WR#D7:0D/C#RD#highlowF
45、igure 8-3 : Example of Read procedure in 8080 parallel interface mode CS#WR#D7:0D/C#RD#highlowSSD1306 Rev 1.0 P 17/59 Sep 2007 Solomon SystechTable 8-3 : Control pins of 8080 interface Function RD# WR# CS# D/C# Write command H L L Read status H L L Write data H L H Read data H L H Note (1) stands fo
46、r rising edge of signal (2)H stands for HIGH in signal (3)L stands for LOW in signal In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display
47、 data read. This is shown in Figure 8-4. Figure 8-4 : Display data read back procedure - insertion of dummy read N n n+1 n+2WR#RD#DatabusWrite columnaddressRead 1st dataDummy read Read 2nd data Read 3rd data8.1.3 MCU Serial Interface (4-wire SPI) The 4-wire serial interface consists of serial clock:
48、 SCLK, serial data: SDIN, D/C#, CS#. In 4-wire SPI mode, D0 acts as SCLK, D1 acts as SDIN. For the unused data pins, D2 should be left open. The pins from D3 to D7, E and R/W# (WR#)# can be connected to an external ground. Table 8-4 : Control pins of 4-wire Serial interface Function E R/W# CS# D/C#W
49、rite command Tie LOW Tie LOW L L Write data Tie LOW Tie LOW L H Note (1)H stands for HIGH in signal (2) L stands for LOW in signal SDIN is shifted into an 8-bit shift register on every rising edge of SCLK in the order of D7, D6, . D0. D/C# is sampled on every eighth clock and the data byte in the shift register is written to the Graphic Display Data RAM (GDDRAM) or command register in the same clock. Under serial mode, only write operations are allowed. Solomon
