1、REV.0Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third parties thatmay result from its use. No license is granted by implication or otherwis
2、eunder any patent or patent rights of Analog Devices.aADF4106One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/329-Fax: 781/326-8703 Analog Devices, Inc., 2001PLL Frequency SynthesizerFEATURES6.0 GHz Bandwidth2.7 V to 3.3 V Power SupplySeparate Charge Pump Supply (VP) Allows
3、ExtendedTuning Voltage in 3 V SystemsProgrammable Dual Modulus Prescaler8/9, 16/17, 32/33, 64/65Programmable Charge Pump CurrentsProgrammable Anti-Backlash Pulsewidth3-Wire Serial InterfaceAnalog and Digital Lock DetectHardware and Software Power-Down ModeAPPLICATIONSBroadband Wireless AccessInstrum
4、entationWireless LANSBase Stations For Wireless RadioFUNCTIONAL BLOCK DIAGRAM14-BITR COUNTERR COUNTERLATCHFUNCTIONLATCHAB COUNTERLATCH24-BIT INPUTREGISTER2214REFINCLKDATALEAVDDDVDDPHASEFREQUENCYDETECTORCHARGEPUMPREFERENCEVPCPGND RSETCURRENTSETTING 2CURRENTSETTING 1CPI3 CPI2 CPI1 CPI6 CPI5 CPI4LOCKDE
5、TECTCPMUXOUTAVDDSDOUTHIGH Z1913-BITB COUNTERPRESCALERP/P + 1RFINARFINB6-BITA COUNTERFROMFUNCTIONLATCHLOADLOADM3 M2 M1MUX6N = BP + ACE AGND DGNDADF410613GENERAL DESCRIPTIONThe ADF4106 frequency synthesizer can be used to implementlocal oscillators in the up-conversion and down-conversionsections of w
6、ireless receivers and transmitters. It consists of alow-noise digital PFD (Phase Frequency Detector), a precisioncharge pump, a programmable reference divider, programmableA and B counters and a dual-modulus prescaler (P/P + 1). TheA (6-bit) and B (13-bit) counters, in conjunction with the dualmodul
7、us prescaler (P/P + 1), implement an N divider (N = BP + A).In addition, the 14-bit reference counter (R Counter), allowsselectable REFIN frequencies at the PFD input. A completePLL (Phase-Locked Loop) can be implemented if the synthe-sizer is used with an external loop filter and VCO (VoltageContro
8、lled Oscillator). Its very high bandwidth means thatfrequency doublers can be eliminated in many high-frequencysystems, simplifying system architecture and lowering cost.REV. 02ADF4106SPECIFICATIONS1BChips2Parameter B Version1(typ) Unit Test Conditions/CommentsRF CHARACTERISTICS See Figure 3 for Inp
9、ut CircuitRF Input Frequency (RFIN)30.5/6.0 0.5/6.0 GHz min/maxRF Input Sensitivity 10/0 10/0 dBm min/maxMaximum AllowablePrescaler Output Frequency4300 300 MHz maxREFIN CHARACTERISTICSREFIN Input Frequency 20/250 20/250 MHz min/max For f 20 MHz, Use DC-CoupledSquare Wave, (0 to VDD)REFIN Input Sens
10、itivity50.8/AVDD0.8/AVDDV p-p min/max AC-Coupled; When DC-Coupled,0 to VDDmax (CMOS Compatible)REFIN Input Capacitance 10 10 pF maxREFIN Input Current 100 100 A maxPHASE DETECTORPhase Detector Frequency656 56 MHz maxCHARGE PUMPICPSink/Source Programmable, See Table VHigh Value 5 5 mA typ With RSET=
11、5.1 kLow Value 625 625 A typAbsolute Accuracy 2.5 2.5 % typ With RSET= 5.1 kRSETRange 2.7/10 2.7/10 k typ See Table VICPThree-State Leakage Current 1 1 nA typSink and Source Current Matching 2 2 % typ 0.5 V H11349 VCPH11349 VP 0.5 VICPvs. VCP1.5 1.5 % typ 0.5 V H11349 VCPH11349 VP 0.5 VICPvs. Temper
12、ature 2 2 % typ VCP= VP/2LOGIC INPUTSVINH, Input High Voltage 1.4 1.4 V minVINL, Input Low Voltage 0.6 0.6 V maxIINH/IINL, Input Current 1 1 A maxCIN, Input Capacitance 10 10 pF maxLOGIC OUTPUTSVOH, Output High Voltage 1.4 1.4 V min Open Drain Output Chosen 1 kPull-up to 1.8 VVOH, Output High Voltag
13、e 1.4 1.4 V min CMOS Output ChosenIOH100 100 A maxVOL, Output Low Voltage 0.4 0.4 V max IOL= 500 APOWER SUPPLIESAVDD2.7/3.3 2.7/3.3 V min/V maxDVDDAVDDAVDDVPAVDD/5.5 AVDD/5.5 V min/V max AVDDH11349 VPH11349 5.5 VIDD7 (AIDD+ DIDD) 15 13 mA max 13 mA typIP0.4 0.4 mA max TA= 25CPower-Down Mode8(AIDD+ D
14、IDD)10 10 A typ(AVDD = DVDD= 3 V H11550 10%; AVDD VP 5.5 V; AGND = DGND = CPGND = 0 V;RSET= 5.1 kH9024; dBm referred to 50 H9024; TA= TMINto TMAXunless otherwise noted.)3REV. 0BChips2Parameter B Version1(typ) Unit Test Conditions/CommentsNOISE CHARACTERISTICSADF4106 Phase Noise Floor9174 174 dBc/Hz
15、typ 25 kHz PFD Frequency166 166 dBc/Hz typ 200 kHz PFD Frequency159 159 dBc/Hz typ 1 MHz PFD FrequencyPhase Noise Performance10 VCO Output900 MHz Output1193 93 dBc/Hz typ 1 kHz Offset and 200 kHz PFD Frequency5800 MHz Output1274 74 dBc/Hz typ 1 kHz Offset and 200 kHz PFD Frequency5800 MHz Output1384
16、 84 dBc/Hz typ 1 kHz Offset and 1 MHz PFD FrequencySpurious Signals900 MHz Output1190/92 90/92 dBc typ 200 kHz/400 kHz and 200 kHz PFD Frequency5800 MHz Output1265/70 65/70 dBc typ 200 kHz/400 kHz and 200 kHz PFD Frequency5800 MHz Output1370/75 70/75 dBc typ 1 MHz/2 MHz and 1 MHz PFD FrequencyNOTES1
17、Operating temperature range (B Version) is 40C to +85C.2The BChip specifications are given as typical values.3Use a square wave for lower frequencies, below the mimimum stated.4This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF in
18、put is divided down to a frequencythat is less than this value.5AVDD= DVDD= 3 V6Guaranteed by design. Sample tested to ensure compliance.7TA= 25C; AVDD= DVDD= 3 V; P = 16; RFIN= 6.0 GHz8TA= 25C; AVDD= DVDD= 3.3 V; R = 16383; A = 63; B = 891; P = 32; RFIN= 6.0 GHz9The synthesizer phase noise floor is
19、 estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).10The phase noise is measured with the EVAL-ADF4106EB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN forthe synthesizer (fRE
20、FOUT= 10 MHz 0 dBm).11fREFIN= 10 MHz; fPFD= 200 kHz; Offset Frequency = 1 kHz; fRF= 900 MHz; N = 4500; Loop B/W = 20 kHz12fREFIN= 10 MHz; fPFD= 200 kHz; Offset Frequency = 1 kHz; fRF= 5800 MHz; N = 29000; Loop B/W = 20 kHz13fREFIN= 10 MHz; fPFD= 1 MHz; Offset Frequency = 1 kHz; fRF= 5800 MHz; N = 58
21、00; Loop B/W = 100 kHzSpecifications subject to change without notice.(AVDD = DVDD= 3 V H11549 10%; AVDD VP 5.5 V; AGND = DGND = CPGND = 0 V; RSET= 5.1 kH9024;TA= TMINto TMAXunless otherwise noted.)CLOCKDB23 (MSB) DB22 DB2DB1 (CONTROLBIT C2)t5DATALEDB0 (LSB)(CONTROL BIT C1) t6t1t2t3t4LEFigure 1. Tim
22、ing DiagramTIMING CHARACTERISTICSLimit atTMINto TMAXParameter (B Version) Unit Test Conditions/Commentst110 ns min DATA to CLOCK Setup Timet210 ns min DATA to CLOCK Hold Timet325 ns min CLOCK High Durationt425 ns min CLOCK Low Durationt510 ns min CLOCK to LE Setup Timet620 ns min LE PulsewidthGuaran
23、teed by design but not production tested.ADF4106REV. 0ADF41064ABSOLUTE MAXIMUM RATINGS1, 2(TA= 25C unless otherwise noted.)AVDDto GND3. . . . . . . . . . . . . . . . . . . . . . 0.3 V to +3.6 VAVDDto DVDD. . . . . . . . . . . . . . . . . . . . . . 0.3 V to +0.3 VVPto GND . . . . . . . . . . . . . .
24、. . . . . . . . . . . 0.3 V to +5.3 VVPto AVDD. . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +5.5 VDigital I/O Voltage to GND . . . . . . . . 0.3 V to VDD+ 0.3 VAnalog I/O Voltage to GND . . . . . . . . . 0.3 V to VP+ 0.3 VREFIN, RFINA, RFINB to GND . . . . . . 0.3 V to VDD+ 0.3 VOperati
25、ng Temperature RangeIndustrial (B Version) . . . . . . . . . . . . . . . 40C to +85CStorage Temperature Range . . . . . . . . . . . . 65C to +150CMaximum Junction Temperature . . . . . . . . . . . . . . . . 150CTSSOP H9258JAThermal Impedance . . . . . . . . . . . . . 150.4C/WCSP H9258JAThermal Imped
26、ance . . . . . . . . . . . . . . . . . . 122C/WLead Temperature, SolderingVapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215CInfrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220CNOTES1Stresses above those listed under Absolute Maximum Ratings may cause
27、perma-nent damage to the device. This is a stress rating only; functional operation of thedevice at these or any other conditions above those listed in the operationalsections of this specification is not implied. Exposure to absolute maximum ratingconditions for extended periods may affect device r
28、eliability.2This device is a high-performance RF integrated circuit with an ESD rating of2 kV and it is ESD sensitive. Proper precautions should be taken for handling andassembly.3GND = AGND = DGND = 0 VORDERING GUIDEModel Temperature Range Package Option*ADF4106BRU 40C to +85C RU-16ADF4106BCP 40C t
29、o +85C CP-20*RU = Thin Shrink Small Outline Package (TSSOP)CP = Chip Scale PackageContact the factory for chip availability.Note that aluminum bond wire should not be used with the ADF4106 die.CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readilyaccum
30、ulate on the human body and test equipment and can discharge without detection. Although theADF4106 features proprietary ESD protection circuitry, permanent damage may occur on devicessubjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommendedto avoid perform
31、ance degradation or loss of functionality.WARNING!ESD SENSITIVE DEVICEREV. 0ADF41065PIN CONFIGURATIONSPIN FUNCTION DESCRIPTIONSMnemonic FunctionRSETConnecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominalvoltage potential at the RSETpin is 0.6 V. The
32、relationship between ICPand RSETisIRCP MAXSET=25 5.So, with RSET= 5.1 k, ICPMAX= 5 mA.CP Charge Pump Output. When enabled this provides ICPto the external loop filter, which in turn drives theexternal VCO.CPGND Charge Pump Ground. This is the ground return path for the charge pump.AGND Analog Ground
33、. This is the ground return path of the prescaler.RFINB Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypasscapacitor, typically 100 pF. See Figure 3.RFINA Input to the RF Prescaler. This small signal input is ac coupled to the external VCO.AV
34、DDAnalog Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground planeshould be placed as close as possible to this pin. AVDDmust be the same value as DVDD.REFINReference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resi
35、stance of100 k. See Figure 2. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac coupled.DGND Digital GroundCE Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-statemode. Taking the pin high will power up the device de
36、pending on the status of the power-down bit F2.CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.DATA Serial Data Input. The serial data i
37、s loaded MSB first with the two LSBs being the control bits. This input is ahigh impedance CMOS input.LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the fourlatches, the latch being selected using the control bits.MUXOUT This multiplexer o
38、utput allows either the Lock Detect, the scaled RF or the scaled Reference Frequency to beaccessed externally.DVDDDigital Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground planeshould be placed as close as possible to this pin. DVDDmust be the same value a
39、s AVDD.VPCharge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDDis 3 V, it can beset to 5 V and used to drive a VCO with a tuning range of up to 5 V.TSSOPTOP VIEW(Not to Scale)RSETCPCPGNDAGNDRFINBRFINAAVDDREFINVPDVDDMUXOUTLEDATACLKCEDGNDADF410616151413121110912345
40、678Chip Scale Package15 MUXOUT14 LE13 DATA12 CLKCPGND 1AGND 2AGND 320 CP11 CEAVDD6AVDD7REFIN8DGND 9 DGND 10RFINB 4RFINA 519 RSET18 VP17 DVDD16 DVDDPIN 1INDICATORTOP VIEWADF4106NOTE: TRANSISTOR COUNT 6425 (CMOS), 303 (BIPOLAR)REV. 0ADF4106Typical Performance Characteristics6FREQ UNIT GHzPARAM TYPE SD
41、ATA FORMAT MAFREQ MAGS11 ANGS113.300 0.42777 102.7483.400 0.42859 107.1673.500 0.43365 111.8833.600 0.43849 117.5483.700 0.44475 123.8563.800 0.44800 130.3993.900 0.45223 136.7444.000 0.45555 142.7664.100 0.45313 149.2694.200 0.45622 154.8844.300 0.45555 159.6804.400 0.46108 164.9164.500 0.45325 168
42、.4524.600 0.45054 173.4624.700 0.45200 176.6974.800 0.45043 178.8244.900 0.45282 174.9475.000 0.44287 170.2375.100 0.44909 166.6175.200 0.44294 162.7865.300 0.44558 158.7665.400 0.45417 153.1955.500 0.46038 147.7215.600 0.47128 139.7605.700 0.47439 132.6575.800 0.48604 125.7825.900 0.50637 121.1106.
43、000 0.52172 115.400FREQ MAGS11 ANGS110.500 0.89148 17.28200.600 0.88133 20.69190.700 0.87152 24.53860.800 0.85855 27.32280.900 0.84911 31.06981.000 0.83512 34.86231.100 0.82374 38.55741.200 0.80871 41.90931.300 0.79176 45.69901.400 0.77205 49.41851.500 0.75696 52.88981.600 0.74234 56.29231.700 0.722
44、39 60.25841.800 0.69419 63.14461.900 0.67288 65.64642.000 0.66227 68.07422.100 0.64758 71.35302.200 0.62454 75.56582.300 0.59466 79.64042.400 0.55932 82.82462.500 0.52256 85.27952.600 0.48754 85.62982.700 0.46411 86.18542.800 0.45776 86.49972.900 0.44859 88.80803.000 0.44588 91.97373.100 0.43810 95.
45、40873.200 0.43269 99.1282KEYWORD RIMPEDANCE H9024 50TPC 1. S-Parameter Data for the RF InputRF INPUT FREQUENCY GHz00130OUTPUT POWER dB 24651025203155VDD= 3VVP= 3VTA= +85H11543CTA= +25H11543CTA= 40H11543CTPC 2. Input SensitivityFREQUENCY0602kHzOUTPUT POWER dB10507090304080202kHz900MHz1kHz 1kHzREF LEV
46、EL = 14.3dBmVDD= 3V, VP= 5VICP= 5mAPFD FREQUENCY = 200kHzLOOP BANDWIDTH = 20kHzRES BANDWIDTH = 10HzVIDEO BANDWIDTH = 10HzSWEEP = 1.9 SECONDSAVERAGES = 1093.0dBc/Hz100TPC 3. Phase Noise (900MHz, 200kHz, and 20kHz)FREQUENCY OFFSET FROM 900MHz CARRIER100Hz 1MHzPHASE NOISE dBc/Hz405060708090100110120130
47、10dB/DIVRL= 40dBc/HzRMS NOISE = 0.36140TPC 4. Integrated Phase Noise (900 MHz,200kHz, and 20 kHz)FREQUENCY060400kHzOUTPUT POWER dB1050709030408020400kHz900MHz200kHz 200kHzREF LEVEL = 14.0dBmVDD= 3V, VP= 5VICP= 5mAPFD FREQUENCY = 200kHzLOOP BANDWIDTH = 20kHzRES BANDWIDTH = 1kHzVIDEO BANDWIDTH = 1kHzS
48、WEEP = 2.5 SECONDSAVERAGES = 3091.0dBc/Hz100TPC 5. Reference Spurs (900 MHz, 200kHz, and 20 kHz)FREQUENCY0602kHzOUTPUT POWER dB10507090304080202kHz5800MHz1kHz 1kHzREF LEVEL = 10dBmVDD= 3V, VP= 5VICP= 5mAPFD FREQUENCY = 1MHzLOOP BANDWIDTH = 100kHzRES BANDWIDTH = 10HzVIDEO BANDWIDTH = 10HzSWEEP = 1.9 SECONDSAVERAGES = 1084.0dBc/Hz100TPC 6. Phase Noise (5.8GHz, 1MHz, and 100kHz)REV. 0 7ADF4106FREQUENCY OFFSET FROM 5800MHz CARRIER100Hz 1MHzPHASE NOISE dBc/Hz40501406070809010011012013010dB/DIVRL= 40dBc/HzRMS NOISE = 1.8TPC 7. Integrated Phase Noise (5.8 GHz, 1 MHz, and100 kHz)060100
