1、Power Converter Design Using the Saber Simulator A Step-By-Step Guide to the Design of aTwo-Switch, Voltage-Mode, Forward ConverterUsing the Saber SimulatorBy Steve ChwirkaAnalogy, Inc.Beaverton, Oregon(503) 626-9700Page 1 of 32Page 2 of 32Table of Content1.0 Scope of Document 32.0 Specifications 32
2、.1 Input Specifications 32.2 Output Specifications 32.3 Other Specifications 33.0 Step-By-Step Design Process 43.1 Open Loop Design 43.1.1 Define the Duty Cycle and Turns Ratio of the Transformer 43.1.2 Design the Rectifier and Filter Capacitor (Optional Section) 5Validate the Rectifier and Filter C
3、apacitor using Saber 93.1.3 Output Filter Design 10Inductor Design 10Capacitor Design 113.1.4 Validate the Open Loop Design using Saber 113.2 Compensator Design using an Averaged Model 153.2.1 Validate the Averaged Model using Saber 163.2.2 Open-Loop AC Analysis 183.2.3 Designing the Compensation Ci
4、rcuit 183.2.4 Validate the Compensator Design using Saber 213.2.5 Validate the Closed Loop Parameters using Saber 213.3 Modulator Design and Final Closed Loop Simulation 233.3.1 Validate the Modulator Design using Saber 253.3.2 Validate the Closed Loop Design using Saber 273.4 Final Component Level
5、Design 291.0 Scope of DocumentThis engineering document will guide the reader through the step-by-step design of a two switch, voltage mode, forward power converter using the Saber Simulator. In the process, we will describe typical design considerations and problems and how to overcome them. Valida
6、tion of each step in the design process will be performed using Saber.2.0 SpecificationsThe following specifications will be used to design the power converter.2.1 Input SpecificationsLine Input 150Vdc, 6VPin(max) = = 30/.85 35 Watts2.2 Output SpecificationsVout15VdcVout(ripple) 25mV p-pIout 50mA to
7、 2AIout(ripple) 100mA p-pPout(max) = (15V)(2A) 30 Watts2.3 Other SpecificationsEfficiency 85%Switching Frequency 200KHz (derived)Pout(max)EffPage 3 of 323.0 Step-By-Step Design ProcessThis section details the steps necessary to design the power converter.3.1 Open Loop Design3.1.1 Define the Duty Cyc
8、le and Turns Ratio of the TransformerThe basic relationship in a forward converter isVout (Vin)(1 / n)(D) whereVout =dc output voltagen = turns ratio = np/ nsD = duty cycleGiven that Vout = 15VDC and Vin = 150 VDC, we see that (1 / n)(D) must equal 0.1i.e. 15 = (150)(.1)The duty cycle of a forward c
9、onverter should not exceed .5. Therefore we will choose a value which is between 0 and 0.5. In this example we choose D = 0.3, approximately the midpoint of the range.Therefore we know (1 / n)(D) = .1or 1 / n = .1 / D = .1 / .3 = 1/3so n = 3The next step is to define the maximum and nominal duty cyc
10、le which include the output diode losses. These values will be needed for future calculations. n = turns ration = np / ns = 3Vin(min)= 144 (per specifications)Vout = 15V + (output diode losses .85V) = 15.85V Dmax = 15.85 / (144)(1/3) = .3302Note that this is less than .5, the maximum duty cycle allo
11、wed in a forward converter.Dmax = Vout(Vin(min)(1/n)Page 4 of 32Vin(nom)= 150Vdc Dnom = 15.85 / (150)(1/3) = .317Note that this is greater than .3 calculated earlier because it takes the output diode into account.3.1.2 Design the Rectifier and Filter Capacitor (Optional Section)Note: A full-wave bri
12、dge rectifier will be used to allow the design of a smaller filter capacitor.FIGURE 1 shows the rectified waveform, the desired DC input voltage of 150VDC and the result-ing input ripple voltage (Vr).From FIGURE 1:Vpeak = Vin(ac) / .707 = 115 / .707 = 162.7162.7 - (rectifier diode drops) 161.3V (whe
13、re Vd .7)Vdc = 150 VVmin= Vdc - (Vpeak - Vdc) = 150 - (161.3 - 150) = 138.7VDnom = Vout Vin(nom)(1/n)Vr11.311.3VpeakVdcVmint1 t2T3Rectified input voltagewith filter capacitorRectified input voltagewithout filter capacitorFIGURE 1 Filtering of Rectified Input VoltagePage 5 of 32The input filter capac
14、itor value can be found in two waysInput Capacitor Value - Method 1C = (Idc)(T3) / VrIdc= Pin(max) / Vdc = 35W / 150V = .233AVr = (2)(Vpeak-Vdc) = (2)(11.3) = 22.6VT3 = Time the capacitor must deliver its energy to the circuitSolving for T3:T3 = t1 + t2t1 = (1/4)(1/f) where f = input frequency = 60H
15、z= (1/4)(1/60) = 4.166 msecNote: Most text books at this point assume that the input ripple is small and therefore that t2 t1 which would yieldT3 = 4.166 msec + 4.166 msec = 8.33 msecHowever, this is not the case in many designs. Therefore we need to use the following equations to calculate t2:Refer
16、ring to FIGURE 1:Vmin = Vpeak(Sin) = = Sin-1(138.7 / 161.3) = 59.3oWe know that where f = input freq = 60Hz = (59.3)(1/2)(1/60) / 180ot2 = 2.745 msecSin-1Vmin Vpeak180o(1/2) (1/f)= t2t2 = ()(1/2)(1/f)180oPage 6 of 32In other words: From input filter capacitor design equations we hadC = (Idc)(T3)/ Vr
17、Vr = 22.6VIdc = .233AT3 = t1 + t2t1 = 4.166 msect2 = 2.745 msec T3 = 4.166 msec + 2.745 msec = 6.911 msecNote the significant difference between 6.911 msec and the approximate calcula-tion of 8.33 msec.Final Calculation: C = (.233A)(6.9116 msec) / 22.6 V = 71.36 uFInput Capacitor Value - Method 2Usi
18、ng E = CV2 / 2= 71.36 uFt2 = Sin-1Vmin Vpeak121f180oC = (Pin(max)(T3)(1/2)(Vpeak2- Vmin2)= (35)(6.9116m)(1/2)(161.32 - 138.72)Page 7 of 32Once the filter capacitor has been calculated, validate using the schematic shown in Figure 2.This shows a71 an input source:v.* m p = tran=(sin=(va=162.7, f=60)n
19、ote: 115VAC / .707 = 162.7Vpeaka71 filter capacitor with value of 71.36 uF as calculateda71 load resistor which forces Pin(max) = 35WP = V2 / R R = V2 / P = (150)2/ 35 = 642.8 FIGURE 2 Circuit Used to Verify the Rectification and Filter Capacitance for a 35 Watt 115 Vac InputPage 8 of 323.1.2.1 Vali
20、date the Rectifier and Filter Capacitor using SaberView the results shown in Figure 3 and compare with the calculated values.Note: Vpeak 161.3Vmin 138.7Voltage across the input filter capacitor(V):t(s) (1)p76m 78m 80m 82m 84m 86m 88m 90m 92m 94m 96mt(s)138140142144146148150152154156158160162(V)FIGUR
21、E 3 Voltage Across the Input Filter CapacitorPage 9 of 323.1.3 Output Filter DesignThis section will describe the design of the output filter which consist of a 2-pole LC design. The output inductor will be calculated to limit the peak-to-peak ripple current, and the output capacitor will be calcula
22、ted to limit the peak-to-peak output ripple voltage.3.1.3.1 Inductor DesignThe current waveform through the filter inductor is shown in Figure 4.The allowed peak-to-peak current in the inductor is determined by the minimum load current specification. From the spec. we have Iout(min) = .05A. If the l
23、oad current goes below .05A, the converter will go into discontinuous mode (the inductor current goes to zero). See Figure 5.Io = 2 A (max)Iripple tofftoff(max) = 1 - D(min)fswitchingwhere fswitching= 200 KHzFIGURE 4 Current through the Filter InductorIo(min) = .05AMax Ripple CurrentMax Ripple Curre
24、nt Allowed= (2)(Io(min)= (2)(50mA)= 100mA p-pdidt(A)(t)FIGURE 5 Current Through Filter Inductor .05A0.1APage 10 of 32From Figure 4, it can be seen that the inductors current decreases during the OFF time of the switch. In order to prevent discontinuous operation, the inductor current must not go to
25、zero dur-ing this OFF time (at minimum load of .05A per the spec.)Therefore the inductor will be sized to limit the peak-to-peak current to .1A p-p.We know VL= L (di/dt)L = VL/ (di/dt)where VL= 15Vdt = max off time (see Figure 4)=(1 - Dmin) / (f switching)= (1-0.3030) / 200KHz 3.5 usdi = .1A L = 15
26、/ (.1 / 3.5u) .53 mH3.1.3.2 Capacitor DesignThe Vout(ripple) specification, along with the calculated ripple current coming through the induc-tor, determine the size of the output capacitor.The following is used to calculate the capacitor value:Iripple = .1Af = 200KHzVripple = .025V (from spec) C =
27、(1/8) (.1) / (200K)(.025) = 2.5 uFNote that the ESR of the capacitor must not exceed:ESRmax = V / I = .025 / .1 = 0.25or the ripple voltage will increase.3.1.4 Validate the Open Loop Design using Saber Figure 6 shows the Open Loop configurationC = Iripple (1/8)(f)(Vripple)Page 11 of 32This is the Op
28、en Loop configuration of the Forward (two switch) converter. It is used to design the transformers turns ratio and Inductance, the output filter, the Duty Cycle and switching fre-quency. The Open Loop design can then be simulated and validated to make sure the output volt-age is correct based on a c
29、ertain Duty Cycle, the output ripple voltage & ripple current are correct, etc. Note: nominal values for input voltage = 150Vdcmax output current for load = 2A (Rload = 7.5)duty cycle = nominal = .317switching frequency = 200kHzvalues for L, C, ESRRun transient analysisCheck: with Vin = 150V, D = .3
30、17, n = 3, Vout should be 15VILripple should be .1A p-pVout ripple should be approx. .025V p-pFIGURE 6 Open Loop Configuration of the Forward ConverterPage 12 of 32Figure 7 shows the results of the Open Loop simulation. Note that this validates the transformers turns ratio, the output filter design,
31、 duty cycle, and switching frequency.Figure 8 shows an expanded view of the inductor current and validates the ripple current (100mA p-p). Figure 9 shows an expanded view of the output voltage and validates the ripple voltage (25mV p-p)FIGURE 7 Open Loop Simulation ResultsSimulation Results for the
32、Forward, Voltage Mode, Open Loop circuit(A): t(s) (1)i(l.l1)(V): t(s) (1)vout0 50u 100u 150u 200u 250u 300u 350u 400u 450u 500ut(s)-200m0200m400m600m800m11.21.41.61.822.2(A)-4-202468101214161820(V)Inductor currentOutput VoltagePage 13 of 32FIGURE 8 Inductor Ripple Current Simulation Results for the
33、Forward, Voltage Mode, Open Loop circuit(A): t(s) (1)i(l.l1)(V): t(s) (1)vout370u 380u 390u 400u 410u 420u 430u 440u 450u 460u 470ut(s)1.8251.851.8751.91.9251.951.97522.0252.052.0752.12.1252.15(A)16.2516.516.751717.2517.517.751818.2518.518.751919.2519.5(V)Simulation Results for the Forward, Voltage
34、Mode, Open Loop circuit(A):t(s) (1)i(l.l1)(V):t(s) (1)vout370u 380u 390u 400u 410u 420u 430u 440u 450u 460u 470u 480u 490u 500ut(s)1.6751.681.6851.691.6951.71.7051.711.7151.72(A)14.7514.814.8514.914.951515.0515.115.1515.2(V)FIGURE 9 Output Ripple voltagePage 14 of 323.2 Compensator Design using an A
35、veraged ModelThe averaged circuit shown in Figure 10 lets you analyze the power supply without its switching circuitry. Using this averaged circuit, you can perform three types of simulations: an open-loop transient analysis, an open-loop small-signal AC analysis, and a closed-loop analysis. These s
36、im-ulations will provide the needed information to design and validate the compensation circuit.This configuration is use to perform several simulations/analyses. The designer can first perform an open loop transient simulation to validate that the average model is providing the correct out-put volt
37、age for a given control voltage. This transient simulation is also used to set up the operat-ing point for the small signal AC simulation. The next simulation performed is a small signal ac to evaluate the “Control to Output” transfer function. The results are used to design the compensa-tor circuit
38、. Once the compensator circuit is designed, it can be included in another small signal ac simulation to validate the compensator and the feedback has the correct frequency response. The final simulation which can be done from this schematic is a closed loop transient analysis. This will validate tha
39、t the closed loop circuit (using the averaged model) yields the correct control voltage and Duty cycle as expected by the designer.FIGURE 10 Averaged Configuration of the Forward ConverterPage 15 of 32To determine the control voltage for the input to the averaged model, the following control-to-out-
40、put relationship for the forward converter is used: where Vout= 15VVin= 150Vn = 3Vramp= 2.5VVd= 0.85VRearrange the equation to determine the control voltage: 3.2.1 Validate the Averaged Model using Saber Using the Saber simulator and the averaged circuit shown in Figure 10, an open-loop transient an
41、alysis is performed to verify the averaged model, and to set up the operating point for the small signal ac simulation. The results are plotted along with the results from the open loop circuit sim-ulation and are both shown in Figure 11. Note the averaged model results track the switching cir-cuit
42、results very well.VoutVin1n-VcVramp-Vd=VcVrampnVoutVd+Vin- 0.7925=FIGURE 11 Averaged Model vs. Switching Circuit Simulation Results for the Forward, Voltage Mode, Averaged circuit(A): t(s) (6)i(l.l1) (8)i(l.l1)(V) : t(s) (6)vout (8)vout0 50u 100u 150u 200u 250u 300u 350u 400u 450u 500u t(s)-200m0200
43、m400m600m800m11.21.41.61.822.2(A)-4-202468101214161820(V)Inductor CurrentOutput VoltagePage 16 of 32Figure 12 shows the expanded view for the inductor current. Figure 13 shows the expanded view for the output voltage.FIGURE 12 Inductor Current (Switching vs. Averaged)Simulation Results for the Forwa
44、rd, Voltage Mode, Averaged circuit(A): t(s) (6)i(l.l1) (8)i(l.l1)(V): t(s) (6)vout (8)vout160u 180u 200u 220u 240u 260u 280u 300u 320u 340u 360u 380u 400ut(s)1.8251.851.8751.91.9251.951.97522.0252.052.0752.12.125(A)16.2516.516.751717.2517.517.751818.2518.518.751919.25(V)FIGURE 13 Output Voltage (Swi
45、tching vs. Averaged)Simulation Results for the Forward, Voltage Mode, Averaged circuit(A): t(s) (6)i(l.l1) (8)i(l.l1)(V): t(s) (6)vout (8)vout150u 175u 200u 225u 250u 275u 300u 325u 350u 375u 400u 425u 450u 475u 500ut(s)1.651.6551.661.6651.671.6751.681.6851.691.6951.71.705(A)14.614.6514.714.7514.814
46、.8514.914.951515.0515.115.15(V)Page 17 of 323.2.2 Open-Loop AC AnalysisThe next simulation performed using the averaged circuit is an open loop small signal ac analysis. The results are used to evaluate the control-to-output transfer function. This information is then used to design the compensator
47、circuit. Figure 14 shows the frequency response of the control-to-output transfer function. It can be seen that the output filter yields a two pole roll off and a phase of close to 180 degrees:3.2.3 Designing the Compensation CircuitThe compensator design will yield a 0dB crossover at approximately
48、one quarter the switching frequency, and compensate the two-pole roll-off (180 phase) to approximate a single-pole roll-off (90 phase). The compensator will need two zeros to cancel out the effects of the two poles of the output filter. The frequency of the two zeros will be one-half the resonant fr
49、equency of the fil-ter. The compensator will add in another pole at one-quarter the switching frequency, which can-cels the effects of the ESR of the capacitor (zero). The approximate net results yield a single-pole roll-off at the crossover frequency. Phase/Gain plot of the “Control voltage to Output“ transfer functionDB(V): f(Hz) (4)voutDEG(V): f(Hz) (4)vout100m 1 10 100 1k 10k 100k 1meg 10meg 100megf(Hz)-140-120-100-80-60-40-200204060DB(V)-180-1
