1、library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity bobo isport(clk : in std_logic;en : in std_logic
2、 ;clr : in std_logic ;q: out std_logic_vector(3 downto 0);cout : out std_logic);end bobo;architecture Behavioral of bobo issignal cqi: std_logic_vector(3 downto 0);beginprocess(clk,en,clr)beginif clr=1then cqi0);elsif clk event and clk=1thenif en=1then cqi=cqi+1;end if;end if;if cqi=“1111“ then cout=1;else cout=0;end if;end process;q=cqi;end Behavioral;顶层综合电路图底层
