1、XCHL DSP 1 DSP 2.1 2.2 CPU 2.3 I/O 2.4 2.5 2.6 XCHL DSP 2 2.1 PAB 16 DRAB 16 DWAB 16 PRDB 16 DRDB 16 DWDB 16XCHL DSP 3 DSP CPU Flash ROM ROM 16K RAM S R A M RAM DARAM B0 RAM B0 DARAM B1 B2 RAM B1 B2 XCHL DSP 4 Flash ROM SARAM B0 DARAM B1, B2 DARAM CPU PAB DRAB DWAB PRDB DRDB DWDBXCHL DSP 5 C24X DSP
2、1 P T D E P T D E P 2 P T D E P T D E 3 P T D E P T D 4 P T D E P T P T D E XCHL DSP 6 2.2 CPU C P U DSP C24X CPU C24X DSP CPU C24X DSP CPU ARAU ST 0 ST 1 XCHL DSP 7 PRDB DRDB 16 32 MUX 32 31 16 15 0 PRDB DRDB 16 16 32 16 to CALU XCHL DSP 8 3 2 CALU 3 2 CALU ACCH ACCL C MUX 32 32 32 32 32 32 32 32 1
3、6 XCHL DSP 9 32 1 6 1 6 16 3 2 3 2 TREG 16bit Multiplier 16 16 PREG 32bit MUX Product Shifter 32bit PRDB DRDB DRDB DRDB 16 32 32 16 16 16 16 16 to to CALU XCHL DSP 10 ARAU 8 AR 0 AR 7 A R 0 AR 7 A R A U 3LSB DRDB AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 ARB ARP MUX IR MUX ARAU 16 16 bit, to DWAB 16 bit, to D
4、RDB 16 bit, to DRAB 16 8LSBs 16 3LSBs 3 3 DRDBXCHL DSP 11 ST 0 ST 1 S T 0 b i t 0 8 DP b i t 9 INTM ,INTM=1 b i t 1 0 b i t 1 1 OVM OVM=1 b i t 1 2 OV OV=1 b i t 1 3 1 5 ARP ARP OV OVM 1 INTM DP 1513 12 11 10 9 80XCHL DSP 12 S T 1 b i t 0 1 PM 00 01 0 10 4 0 11 6 b i t 2 3 bit4 XF XF b i t 5 8 b i t
5、 9 C C=0 b i t 1 0 SXM SXM=1 b i t 1 1 TC / b i t 1 2 CNF DARAM CNF=1 B0 b i t 1 3 1 5 ARB ARB CNF TC SXM C 1513 12 11 10 9 85 4 32 10 XF PM XCHL DSP 13 2.3 I/O TMS320C24X DSP 244K 4 64K 64K 32K 64K I/O PAB PRDB I/O DRAB DRDB DWAB DWDB XCHL DSP 14 FLASH ROM 4/8/24/32K Words (External if Mp/MC=1) SAR
6、AM 0/1/2/4/8/16K Words (External if RAMEN=0) External DARAM B0 256/512 words CNF=1 (External if CNF=0) Reserved 0000H 003FH 0040H FDFFH FE00H FEFFH FF00H FFFFH Reset Interrupt level 1 Interrupt level 2 Interrupt level 3 Interrupt level 4 Interrupt level 5 Interrupt level 6 Reserved Software interrup
7、ts TRAP NMI Reserved Software interrupts 0000H 0002H 0004H 0006H 0008H 000AH 000CH 000EH 0010H 0022H 0024H 0026H 0028H 003FHXCHL DSP 15 64K 0000H003FH 0040HFDFFH FE00HFEFFH FF00HFFFFH 0000H3FFFH MP/ MC=0 16K ROM MP/ MC=1 4000HFDFFH FE00HFEFFH CNF=1 MP/ MC=0 DARAM B0 FF00HFFFFH XCHL DSP 16 Reserved D
8、ARAM (B0) 256/512 words CNF=0 Memory-mapped register DARAM (B2) 32 words DARAM(B1) 256/512 words Reserved SARAM 1/2/4/8/16K words Peripheral bus Peripheral frame data bus direct connect Unused External 0000H 005FH 0060H 007FH 0080H 00FFH 0100H 02FFH 0300H 04FFH 0800H 6FFFH 7000H 73FFH 7400H 743FH 80
9、00H FFFFH reserved IMR GREG IFR Emulation registers and reserved 0000H 0003H 0004H 0005H 0006H 0007H 005FH 0080H 00FFH spare WD / RTI / PLL ADCs SPI SCI spare spare I/O spare 7000H 7010H 7020H 7030H 7040H 7050H 7060H 7070H 7080H 7090H 70A0H 7400H 743FH Event ManagerXCHL DSP 17 0000H7FFFH DARAM B 0 2
10、56/512 CNF=0 0100 02FFH CNF=1 FE00HFEFFH B 1 256/512 0300H04FFH B 2 32 0060H007FH SARAM RAMEN=1 RAMEN=0 8000HFFFFH XCHL DSP 18 0000H005FH 0060H007FH DARAM 0080H00FFH 0100H04FFH 0500H07FFH 0800H6FFFH SARAM 7000H743FH 7440H7FFFH 8000HFFFFH XCHL DSP 19 32K 8000HFFFFH 32K 0000H7FFFH 32K BR DS / GREG mem
11、ory allocation register XCHL DSP 20 GREG 0005H 8 GREG GREG XX00H X 0 XX80H 8000HFFFFH 32768 XXC0H C000HFFFFH 16384 XXE0H E000HFFFFH 8192 XXF0H F000HFFFFH 4096 XXF8H F800HFFFFH 2048 XXFCH FC00HFFFFH 1024 XXFEH FE00HFFFFH 512 XXFFH FF00HFFFFH 256 XCHL DSP 21 8K GREG XXE0H Lower 32K 16 (always local) U
12、pper 32K 16 (local and/or global) 0000H 7FFFH 8000H FFFFH Data memory map Local 24K 16 Global 8K 16 8000H DFFFH E000H FFFFH GREG=XXE0H XCHL DSP 22 I/O 64K 0000HFFFFH 0000HFEFFH I/O FF00HFFFEH WEGR FFFFH in out IS External I/O mapped register WSGR 0000H FEFFH FF00H FFFEH FFFFH XCHL DSP 23 2.4 OSCBYP
13、XTAL1 1 XTAL2 2 XTAL1/CLKIN XTAL2 OSCBYP +5V XTAL1/CLKIN XTAL2 OSCBYP XCHL DSP 24 CPUCLK XTAL OSC MUX Div2 Div2 MUX VCO 1 2 3 4 5 9 SYSCLK 1MHz PLL CKCR1.07 CKCR0.O ACLK WDCLK SYSCLK CKCR0.76) PLLXCHL DSP 25 CPUCLK CPU / CPU PLL SYSCLK CPU 2 4 ACLK 1 10 MHz WDCLK 16384Hz 25 XCHL DSP 26 CKCR0 CKCR1 C
14、KCR0 (702BH) CLKMD1 CLKMD0 158 7 6 5 4 3 2 1 0 PLLOCK1 PLLOCK0 PLLPM1 PLLPM0 ACLKENA PLLPS CKINF3 CKINF2 158 7 6 5 4 3 2 1 0 CKINF1 CKINF0 PLLDIV PLLFB2 PLLFB1 PLLFB0 CKCR1 (702DH) XCHL DSP 27 2.5 PORESET RS C N F = 0 I N T M = 1 OV=0,XF=1,SXM=1,PM=00, G R E G PRTC=0 1 WDRST RS SWRST ILLADR Pin RS t
15、o device Reset signal PORST/VCCAORXCHL DSP 28 SYSCR (7018H) RESET1 RESET0 CLKSRC1 CLKSRC0 15 14 13 8 7 6 50 SYSSR (701AH) PORST ILLADR 15 14 13 12 11 10 9 8 6 5 4 3 2 1 0 SWRST WDRST HPO VECRD VCCAOR XCHL DSP 29 2.6 PC PC+1 PAR PRDB( DRDB 16 TOS PRDB MSTACK 16 8 PUSH POP PSHD POPD MSTACK 16 1 BLDD B
16、LPD MAC MACD TBLR TBLW 30 MUX Sequential operation PC+1/NPAR+1 Dummy cycle PAR Table / block move MSTACK Next program address Register (NPAR) MUX Program control Top of stack TOS) Program address Stack 8 16 PRDB DRDB DWAB PAB PSHD instruction POPD instruction BACC or CALA instruction Interrupt branch or call
