1、W25Q64FW Publication Release Date: August 14, 2014 Revision G 1.8V 64M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI W25Q64FW - 1 - Table of Contents 1. GENERAL DESCRIPTIONS . 4 2. FEATURES . 4 3. PACKAGE TYPES AND PIN CONFIGURATIONS 5 3.1 Pin Configuration SOIC / VSOP 208-mil 5 3.2 Pad Configura
2、tion WSON 6x5-mm 5 3.3 Pin Description SOIC/VSOP 208-mil, WSON 6x5-mm 5 3.4 Ball Configuration WLCSP . 6 3.5 Ball Description WLCSP . 6 4. PIN DESCRIPTIONS 7 4.1 Chip Select (/CS) 7 4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) 7 4.3 Write Protect (/WP). 7 4.4 HOLD (/HOLD) .
3、7 4.5 Serial Clock (CLK) 7 4.6 Reset (/RESET) 7 5. BLOCK DIAGRAM 8 6. FUNCTIONAL DESCRIPTIONS . 9 6.1 SPI / QPI Operations 9 6.1.1 Standard SPI Instructions . 9 6.1.2 Dual SPI Instructions 9 6.1.3 Quad SPI Instructions . 10 6.1.4 QPI Instructions 10 6.1.5 Hold Function 10 6.1.6 Software Reset & Hard
4、ware /RESET pin 11 6.2 Write Protection 12 6.2.1 Write Protect Features 12 7. STATUS AND CONFIGURATION REGISTERS 13 7.1 Status Registers . 13 7.1.1 Erase/Write In Progress (BUSY) Status Only 13 7.1.2 Write Enable Latch (WEL) Status Only 13 7.1.3 Block Protect Bits (BP2, BP1, BP0) Volatile/Non-Volati
5、le Writable 13 7.1.4 Top/Bottom Block Protect (TB) Volatile/Non-Volatile Writable . 14 7.1.5 Sector/Block Protect Bit (SEC) Volatile/Non-Volatile Writable . 14 7.1.6 Complement Protect (CMP) Volatile/Non-Volatile Writable 14 7.1.7 Status Register Protect (SRP1, SRP0) Volatile/Non-Volatile Writable .
6、 14 7.1.8 Erase/Program Suspend Status (SUS) Status Only 15 7.1.9 Security Register Lock Bits (LB3, LB2, LB1) Volatile/Non-Volatile OTP Writable 15 W25Q64FW Publication Release Date: August 14, 2014 - 2 - Revision G 7.1.10 Quad Enable (QE) Volatile/Non-Volatile Writable 15 7.1.11 Write Protect Selec
7、tion (WPS) Volatile/Non-Volatile Writable 16 7.1.12 Output Driver Strength (DRV1, DRV0) Volatile/Non-Volatile Writable . 16 7.1.13 /HOLD or /RESET Pin Function (HOLD/RST) Volatile/Non-Volatile Writable 16 7.1.14 Reserved Bits Non Functional . 16 7.1.15 W25Q64FW Status Register Memory Protection (WPS
8、 = 0, CMP = 0) 17 7.1.16 W25Q64FW Status Register Memory Protection (WPS = 0, CMP = 1) 18 7.1.17 W25Q64FW Individual Block Memory Protection (WPS=1) 19 8. INSTRUCTIONS . 20 8.1 Device ID and Instruction Set Tables . 20 8.1.1 Manufacturer and Device Identification . 20 8.1.2 Instruction Set Table 1 (
9、Standard/Dual/Quad SPI Instructions) (1). 21 8.1.3 Instruction Set Table 2 (Standard/Dual/Quad SPI Instructions) (1). 22 8.1.4 Instruction Set Table 3 (QPI Instructions) (14). 23 8.2 Instruction Descriptions 25 8.2.1 Write Enable (06h) 25 8.2.2 Write Enable for Volatile Status Register (50h) . 25 8.
10、2.3 Write Disable (04h) . 26 8.2.4 Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h) . 26 8.2.5 Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h) . 27 8.2.6 Read Data (03h) . 30 8.2.7 Fast Read (0Bh) . 31 8.2.8 Fast Read Dual Output (3Bh)
11、. 33 8.2.9 Fast Read Quad Output (6Bh) 34 8.2.10 Fast Read Dual I/O (BBh) . 35 8.2.11 Fast Read Quad I/O (EBh) . 37 8.2.12 Word Read Quad I/O (E7h) 40 8.2.13 Octal Word Read Quad I/O (E3h) . 42 8.2.14 Set Burst with Wrap (77h) . 44 8.2.15 Page Program (02h) . 45 8.2.16 Quad Input Page Program (32h)
12、. 47 8.2.17 Sector Erase (20h) 48 8.2.18 32KB Block Erase (52h) 49 8.2.19 64KB Block Erase (D8h) . 50 8.2.20 Chip Erase (C7h / 60h) . 51 8.2.21 Erase / Program Suspend (75h) . 52 8.2.22 Erase / Program Resume (7Ah) 54 8.2.23 Power-down (B9h) 55 8.2.24 Release Power-down / Device ID (ABh) . 56 8.2.25
13、 Read Manufacturer / Device ID (90h) . 58 W25Q64FW - 3 - 8.2.26 Read Manufacturer / Device ID Dual I/O (92h) . 59 8.2.27 Read Manufacturer / Device ID Quad I/O (94h) 60 8.2.28 Read Unique ID Number (4Bh) . 61 8.2.29 Read JEDEC ID (9Fh) 62 8.2.30 Read SFDP Register (5Ah) . 63 8.2.31 Erase Security Re
14、gisters (44h) . 64 8.2.32 Program Security Registers (42h) . 65 8.2.33 Read Security Registers (48h) 66 8.2.34 Set Read Parameters (C0h) . 67 8.2.35 Burst Read with Wrap (0Ch) . 68 8.2.36 Enter QPI Mode (38h) . 69 8.2.37 Exit QPI Mode (FFh) . 70 8.2.38 Individual Block/Sector Lock (36h) 71 8.2.39 In
15、dividual Block/Sector Unlock (39h) 72 8.2.40 Read Block/Sector Lock (3Dh) 73 8.2.41 Global Block/Sector Lock (7Eh) 74 8.2.42 Global Block/Sector Unlock (98h) . 74 8.2.43 Enable Reset (66h) and Reset Device (99h) 75 9. ELECTRICAL CHARACTERISTICS 76 9.1 Absolute Maximum Ratings(1)(2)76 9.2 Operating R
16、anges 76 9.3 Power-up Power-down Timing and Requirements 77 9.4 DC Electrical Characteristics 78 9.5 AC Measurement Conditions . 79 9.6 AC Electrical Characteristics (6,7). 80 9.7 AC Electrical Characteristics (contd) . 81 9.8 Serial Output Timing . 82 9.9 Serial Input Timing 82 9.10 /HOLD Timing .
17、82 9.11 /WP Timing . 82 10. PACKAGE SPECIFICATIONS . 83 10.1 8-Pin SOIC 208-mil (Package Code SS) . 83 10.2 8-Pin VSOP 208-mil (Package Code ST) 84 10.3 8-Pad WSON 6x5-mm (Package Code ZP) . 85 10.4 16-Ball WLCSP (Package Code BY) . 86 11. ORDERING INFORMATION 87 11.1 Valid Part Numbers and Top Side
18、 Marking 88 12. REVISION HISTORY 89 W25Q64FW Publication Release Date: August 14, 2014 - 4 - Revision G 1. GENERAL DESCRIPTIONS The W25Q64FW (64M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance wel
19、l beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single 1.65V to 1.95V power supply with current consumption as low as 4mA active and 1A for power-down. All de
20、vices are offered in space- saving packages. The W25Q64FW array is organized into 32,768 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or th
21、e entire chip (chip erase). The W25Q64FW has 4,096 erasable sectors and 256 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See Figure 2.) The W25Q64FW support the standard Serial Peripheral Interface (SPI),
22、Dual/Quad I/O SPI as well as 2- clocks instruction cycle Quad Peripheral Interface (QPI): Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 104MHz are supported allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O
23、 and 416MHz (104MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O and QPI instructions. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient memory access with as few as 8-clocks of instruction-overhe
24、ad to read a 24-bit address, allowing true XIP (execute in place) operation. A Hold pin, Write Protect pin and programmable write protection, with top or bottom array control, provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device ID, a 64-bit U
25、nique Serial Number and three 256-bytes Security Registers. 2. FEATURES New Family of SpiFlash Memories W25Q64FW: 64M-bit / 8M-byte Standard SPI: CLK, /CS, DI, DO, /WP, /Hold Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3 QPI: CLK, /CS, IO0, IO1, IO2, IO3 Software &
26、Hardware Reset Highest Performance Serial Flash 104MHz Single, Dual/Quad SPI clocks 208/416MHz equivalent Dual/Quad SPI 50MB/S continuous data transfer rate More than 100,000 erase/program cycles More than 20-year data retention Efficient “Continuous Read” and QPI Mode Continuous Read with 8/16/32/6
27、4-Byte Wrap As few as 8 clocks to address memory Quad Peripheral Interface (QPI) reduces instruction overhead Allows true XIP (execute in place) operation Outperforms X16 Parallel Flash Low Power, Wide Temperature Range Single 1.65 to 1.95V supply 4mA active current, 1A Power-down (typ.) -40C to +85
28、C operating range Flexible Architecture with 4KB sectors Uniform Sector/Block Erase (4K/32K/64K-Byte) Program 1 to 256 byte per programmable page Erase/Program Suspend & Resume Advanced Security Features Software and Hardware Write-Protect Power Supply Lock-Down and OTP protection Top/Bottom, Comple
29、ment array protection Individual Block/Sector array protection 64-Bit Unique ID for each device Discoverable Parameters (SFDP) Register 3X256-Bytes Security Registers with OTP locks Volatile & Non-volatile Status Register Bits Space Efficient Packaging 8-pin SOIC/VSOP 208-mil 8-pad WSON 6x5-mm 16-ba
30、ll WLCSP Contact Winbond for KGD and other options W25Q64FW - 5 - 3. PACKAGE TYPES AND PIN CONFIGURATIONS 3.1 Pin Configuration SOIC / VSOP 208-mil 1 2 3 4 8 7 6 5 /CS DO (IO 1 ) /WP (IO 2 ) GND VCC /HOLD or /RESET (IO 3 ) DI (IO 0 ) CLK Top ViewFigure 1a. W25Q64FW Pin Assignments, 8-pin SOIC / VSOP
31、 208-mil (Package Code SS, ST) 3.2 Pad Configuration WSON 6x5-mm 1 2 3 4 /CS DO (IO 1 ) /WP (IO 2 ) GND VCC /HOLD or /RESET (IO 3 ) DI (IO 0 ) CLK Top View8 7 6 5Figure 1b. W25Q64FW Pad Assignments, 8-pad WSON 6x5-mm (Package Code ZP) 3.3 Pin Description SOIC/VSOP 208-mil, WSON 6x5-mm PIN NO. PIN NA
32、ME I/O FUNCTION 1 /CS I Chip Select Input 2 DO (IO1) I/O Data Output (Data Input Output 1) (1)3 /WP (IO2) I/O Write Protect Input ( Data Input Output 2) (2)4 GND Ground 5 DI (IO0) I/O Data Input (Data Input Output 0) (1)6 CLK I Serial Clock Input 7 /HOLD or /RESET (IO3) I/O Hold or Reset Input (Data
33、 Input Output 3) (2)8 VCC Power Supply Notes: 1. IO0 and IO1 are used for Standard and Dual SPI instructions 2. IO0 IO3 are used for Quad SPI instructions, /WP & /HOLD (or /RESET) functions are only available for Standard/Dual SPI. W25Q64FW Publication Release Date: August 14, 2014 - 6 - Revision G
34、3.4 Ball Configuration WLCSP Top View GND DI(IO 0) /CS VCC DO(IO 1) /HOLD(IO 3) /WP(IO 2) CLK A1 B1 C1 D1 A2 B2 C2 D2 A3 B3 C3 D3 A4 B4 C4 D4 NC NC NC NC NC NC NC NC Bottom View GND DI(IO 0) /CS VCC DO(IO 1) /HOLD(IO 3) /WP(IO 2) CLK A1 B1 C1 D1 A2 B2 C2 D2 A3 B3 C3 D3 A4 B4 C4 D4 NC NC NC NC NC NC
35、NC NCFigure 1e. W25Q64FW Ball Assignments, 16-ball WLCSP (Package Code BY) 3.5 Ball Description WLCSP BALL NO. PIN NAME I/O FUNCTION A2 VCC Power Supply B2 /HOLD or /RESET (IO3) I/O Hold or Reset Input (Data Input Output 3) (2)C2 CLK I Serial Clock Input D2 DI (IO0) I/O Data Input (Data Input Output
36、 0) (1)A3 /CS I Chip Select Input B3 DO (IO1) I/O Data Output (Data Input Output 1) (1)C3 /WP (IO2) I/O Write Protect Input (Data Input Output 2) (2)D3 GND Ground Multiple NC No Connect Notes: 1. IO0 and IO1 are used for Standard and Dual SPI instructions 2. IO0 IO3 are used for Quad SPI instruction
37、s, /WP & /HOLD (or /RESET) functions are only available for Standard/Dual SPI. W25Q64FW - 7 - 4. PIN DESCRIPTIONS 4.1 Chip Select (/CS) The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3
38、) pins are at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or write status register cycle is in progress. When /CS is brought low the device will be selected, power consumption will increase to active levels and instructio
39、ns can be written to and data read from the device. After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS input must track the VCC supply level at power-up and power-down (see “Write Protection” and Figure 57). If needed a pull-up resister on the /CS
40、 pin can be used to accomplish this. 4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) The W25Q64FW supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use the unidirectional DI (input) pin to serially write instructions, addresses or data to the dev
41、ice on the rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data or status from the device on the falling edge of CLK. Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or data to the d
42、evice on the rising edge of CLK and read data or status from the device on the falling edge of CLK. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3. 4.3 Write Protect (/WP) The Write Prot
43、ect (/WP) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Registers Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits and Status Register Protect (SRP) bits, a portion as small as a 4KB sector or the entire memory array can be hardware protect
44、ed. The /WP pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the /WP pin function is not available since this pin is used for IO2. See Figure 1a-c for the pin configuration of Quad I/O operation. 4.4 HOLD (/HOLD) The /HOLD pin allows the device to be paused while it is ac
45、tively selected. When /HOLD is brought low, while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored (dont care). When /HOLD is brought high, device operation can resume. The /HOLD function can be useful when multiple devices are sharing the same SPI
46、signals. The /HOLD pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the /HOLD pin function is not available since this pin is used for IO3. See Figure 1a-c for the pin configuration of Quad I/O operation. 4.5 Serial Clock (CLK) The SPI Serial Clock Input (CLK) pin provide
47、s the timing for serial input and output operations. (“See SPI Operations“) 4.6 Reset (/RESET) The /RESET pin allows the device to be reset by the controller. For 8-pin packages, when QE=0, the IO3 pin can be configured either as a /HOLD pin or as a /RESET pin depending on Status Register setting. W
48、hen QE=1, the /HOLD or /RESET function is not available for 8-pin configuration. On the 16-pin SOIC package, a dedicated /RESET pin is provided and it is independent of QE bit setting. W25Q64FW Publication Release Date: August 14, 2014 - 8 - Revision G 5. BLOCK DIAGRAM Figure 2. W25Q64FW Serial Flas
49、h Memory Block Diagram 003000h 0030FFh 002000h 0020FFh 001000h 0010FFh Column Decode And 256-Byte Page Buffer Beginning Page Address Ending Page Address W25Q64FV SPI Command & Control Logic Byte Address Latch / Counter Status Register Write Control Logic Page Address Latch / Counter DO (IO 1 ) DI (IO 0 ) /CS CLK /HOLD (IO 3 ) /WP (IO 2 ) High Voltage Generators xx0F00h xx0FFFh Sector 0 (4KB) xx00
