1、第 9 章 皮尔斯振荡器 Pierce Oscillator (S12XOSCLCPV2)赵洪慷 9.1 Introduction 简介The Pierce oscillator (XOSC) module provides a robust, low-noise and low-power clock source. The module will be operated from the VDDPLL supply rail (1.8 V nominal) and require the minimum number of external components . It is desig
2、ned for optimal start-up margin with typical crystal oscillators.皮尔斯振荡器 (XOSC) 模块提供了一个强健、 低噪音和低功耗的时钟源。这种模型由VDDPLL supply rail (1.8 V nominal)操作并且需要提供扩充组件数量的最小值。它是以典型的晶体振荡器为工具，为最佳的启动 margin 而设计的。它的设计就是为了优化启动边缘有典型的晶体振荡器9.1.1 特点 The XOSC will contain circuitry to dynamically control current gain in the
3、 output amplitude. XOSC 将控制电路系统去动态的控制获取通用的/现在的?输出振幅。 This ensures a signal with low harmonic distortion , low power and good noise immunity.这确保了一个信号能够拥有低和谐的失真 、低能耗并且能够很好的去除噪音等特点。 High noise immunity due to input hysteresis 输入滞后带来高噪音免疫力 Low RF emissions with peak-to-peak swing limited dynamically 低 R
4、F 发射功率被动态限制在尖峰对尖峰上下间摇摆。 Transconductance (gm) sized for optimum start-up margin for typical oscillators. 跨导（GM）为典型振荡器按大小分类以获得最适宜的启动 margin。 Dynamic gain control eliminates the need for external current limiting resistor. 动态收获控制消除对外部 电流限制 限流 电阻器的需求 Integrated resistor eliminates the need for external
5、 bias resistor in loop controlled Pierce mode.在环控制皮尔斯模式中，集成电阻器消除对外部偏离 bias 电阻器的需求。 Low power consumption 低功耗: Operates from 1.8 V (nominal) supply 1.8V 电压支持运行。 Amplitude control limits power 振幅控制限制能量需求。 9.1. 2Modes9.1.2Modes of Operation操作模式Two modes of operation exist两种现存的操作模式1. Loop controlled Pie
6、rce (LCP) oscillator周期控制皮尔斯（ LCP）振荡器2. External square wave mode featuring also full swing Pierce (FSP) without internal bias resistor.外部方波模式也以没有内部偏离电阻器的全振荡皮尔斯（FSP）为特色The oscillator mode selection is described in the Device Overview section, subsection Oscillator。振荡器模式选择在装置综述章节细分振荡器部分描述。Figure 9-1 显
7、示 XOSC 的模块图9.1.3 Block Diagram 模块图Figure 9-1 shows a block diagram of the XOSC.Figure9-1.XOSC Block Diagram9.2 External Signal Description 外部信号描述This section lists and describes the signals that connect off chip本部分列举并描述了芯片间联系的信号9.2.1 VDDPLL and VSSPLL Operating and Ground Voltage PinsVDDPLL和VSSPLL运行
8、和基础电压引脚These pins provides operating voltage (VDDPLL) and ground (VSSPLL) for the XOSC circuitry. This allows the supply voltage to the XOSC to use an independent bypass capacitor. 这些引脚为XOSC电路系统提供运行电压(VDDPLL)和基础(VSSPLL)。这样就让XOSC的供应电压能够使用一个独立的绕行电容器。9.2.2 EXTAL and XTAL Input and Output PinsEXTAL 和XTA
9、L输入输出引脚These pins provide the interface for either a crystal or a 1.8V CMOS compatible clock to control the internal clock generator circuitry. EXTAL is the external clock input or the input to the crystal oscillator amplifier. XTAL is the output of the crystal oscillator amplifier. The MCU internal
10、 system clock is derived from the EXTAL input frequency. In full stop mode(PSTP-0),the EXTAL pin is pulled down by an internal resisitor of typical 200千欧姆.这些引脚为 crystal 或 1.8V CMOS compatible clock 提供控制内部时钟 generator 电路系统的接口。EXTAL 是晶体振荡器放大器的输出。MCU 内置系统时钟由 EXTAL 驶入频率而衍生出。在全等待模式（PSTP-0），EXTAL 引脚被内置的 2
11、00 千欧姆的内置电阻 pull down。NOTEFreescale recommends an evaluation of the application board and chosen resonator or crystal by the resonator or crystal supplier. 注：飞思卡尔建议使用 对应用板和选择共振器或者晶体 进行评估。Loop controlled circuit is not suited for overtone resonators and crystals.周期控制电路不适合于 overtone 共振器和 crystals。Figu
12、re 9-2 Loop Controlled Pierce Oscillator Connections (LCP mode selected)周期控制皮尔斯振荡器连接（选择 LCP 模式）NOTEFull swing Pierce circuit is not suited for overtone resonators and crystalswithout a careful component selection.注：不认真地挑选组件，全振荡皮尔斯电路不适应于 overtone 共振器和晶体 。* Rs can be zero (shorted) when use with highe
13、r frequency crystals.Refer to manufacturers data.MCUFigure 9-3. Full Swing Pierce Oscillator Connections (FSP mode selected)全振荡皮尔斯振荡器连接（选择 FSP 模式）Figure 9-4. External Clock Connections (FSP mode selected) 外部时钟连接（选择 FSP 模式）9.3 Memory Map and Register DefinitionThe CRG contains the registers and assoc
14、iated bits for controlling and monitoring the oscillator module.CRG包含寄存器和与控制监视振荡器模式相关的bits。9.4 Functional Description功能描述The XOSC module has control circuitry to maintain the crystal oscillator circuit voltage level to an optimal level which is determined by the amount of hysteresis being used and t
15、he maximum oscillation range.The oscillator block has two external pins, EXTAL and XTAL. The oscillator input pin, EXTAL, is intended to be connected to either a crystal or an external clock source. The XTAL pin is an output signal that provides crystal circuit feedback.A buffered EXTAL signal becom
16、es the internal clock. To improve noise immunity, the oscillator is powered by the VDDPLL and VSSPLL power supply pins.XOSC 模式使用控制电路来维持晶体振荡器电路电压值在一个最佳的状态，这个最佳电压值由正在被使用的 hyseresis 数量和振荡范围的最大给共同决定。振荡器模块有两个外部引脚，EXTAAL 和 XTAL。输入引脚 EXTAL 是为连接晶体或者外部时钟源而准备，XTAL 是一个输出信号，它提供晶体电路的反馈结果。缓冲 EXTAL 信号成为内部时钟。为了提高噪音
17、免疫力，使用 VDDPLL 和 VSSPLL 供能引脚为振荡器供电。9.4.1 Gain Control 获取控制In LCP mode a closed loop control system will be utilized whereby the amplifier is modulated to keep the output waveform sinusoidal and to limit the oscillation amplitude . The output peak to peak voltage will be kept above twice the maximum h
18、ysteresis level of the input buffer. Electrical specification details are provided in the Electrical Characteristics appendix.。在 LCP 模式，依靠调用放大器来保证正弦波输出和限制振荡振幅，一个闭合周期控制系统被利用。peak to peak 输出电压会被保持在输入缓冲器的最大免疫值两倍以上。电子说细节说明书可参见附录 Electrical Characteristics 。9.4.2 Clock Monitor 时钟监视器The clock monitor circ
19、uit is based on an internal RC time delay so that it can operate without any MCU clocks. If no OSCCLK edges are detected within this RC time delay, the clock monitor indicates failure which asserts self-clock mode or generates a system reset depending on the state of SCME bit . If the clock monitor
20、is disabled or the presence of clocks is detected ， no failure is indicated. The clock monitor function is enabled/disabled by the CME control bit, described in the CRG block description chapter.时钟监视器电路是基于一个内置 RC 时延的，所以它能够在没有 MCU 时钟源的情况下运作。在 PC 时延内，如果没有检测到 OSCCLKedges，时钟监视将会暗示错误声明self_clock 模式或者在 CS
21、ME bit 的状态基础上获取一个系统的重新设置。如果时钟监控不可用或者检测到时钟源，不会引起失败。时钟监控功能由 CME 控制 bit 激活或者挂起，这个在 CRG block 描述章节有详细介绍。9.4.3 Wait Mode Operation 等模式运行During wait mode, XOSC is not impacted.在等模式期间，XOSC 不被嵌入/ 装满。9.4.4 Stop Mode Operation 停止模式运行XOSC is placed in a static state when the part is in stop mode except when pseudo-stop mode is 当部分处在停止模式 stop mode 时， XOSC 将处在静态状态；而当处在 pseudo-stop 模式使除外。
