1、2004-11-14 Liping zhang, Tsinghua Unversity 1 L5q %oMechRabbitGo ahead,make my day!2004-11-14 Liping zhang, Tsinghua Unversity 2 ? 6c q !9 % LZE2004-11-14 Liping zhang, Tsinghua Unversity 3 : 5) Y L : ) 9 1i% y ! 9F H ? : ) ) : 9F “Memory Wait”) ( 7 S | )W ). !9 Ti% v Pi% V H 7Z . | HW : 4-Stage pip
2、eline: 1 clock 5-Stage pipeline: 2 clocks2004-11-14 Liping zhang, Tsinghua Unversity 44-Stage PipelineALUInstructionMemoryADDataMemoryARDWDR/WA BRegisterFileRA1RD1 RD2RA2+4+PCIF1 0 10010 1 24 3 2 1 0WrRA2SELBSELASELWDSELALUFNPCSELZJT00+ 4+ 4Cra rb rcCPCRFIRRFPCALUIRALUA BPCWBIRWBYDALUDWBXPrcIFRFALUW
3、B2004-11-14 Liping zhang, Tsinghua Unversity 55-Stage PipelineALUInstructionMemoryADData MemoryARDWDR/WA BRegisterFileRA1RD1 RD2RA2+4+PCIF1 0 10010 1 24 3 2 1 0RA2SELBSELASELWDSELALUFNPCSELZJT00+ 4+ 4Cra rb rcCPCRFIRRFPCALUIRALUA BPCMEMIRMEMYMEMDALUDMEMXPrcIFRFALUWB Bt% F PCWBIRWBYWBMEMWr2004-11-14
4、Liping zhang, Tsinghua Unversity 6 : Bt “?5 ” Write-Back 1 7WA XH 7W 4-stage L : X = _ write-back delay slot(s) 5-stage L : X = _ write-back delay slots | % 1 when values are read (during RF stage) and2 when values become available (after WB stage) HW s Y H 7 JMP BEQ 7 $ - BEQ, BNE, and JMP: 4-stage
5、 pipeline: Y = _ branch delay slot(s) 5-stage pipeline: Y = _ branch delay slots(s) Y % when target PC becomes decided and available(during RF stage)21312004-11-14 Liping zhang, Tsinghua Unversity 75-Stage PipelineALUInstructionMemoryADData MemoryARDWDR/WA BRegisterFileRA1RD1 RD2RA2+4+PCIF1 0 10010
6、1 24 3 2 1 0RA2SELBSELASELWDSELALUFNPCSELZJT00+ 4+ 4Cra rb rcCPCRFIRRFPCALUIRALUA BPCMEMIRMEMYMEMDALUDMEMXPrcIFRFALUWBPCWBIRWBYWBMEMWr Bt% F 2004-11-14 Liping zhang, Tsinghua Unversity 8q %Z5 qMq 1+YIr B q aB+ L T 9F L)Y ; ? T ? L ; ? 1Ir -_ /_ qY ? 9 ? 7 h“ NOP zE ?2004-11-14 Liping zhang, Tsinghua
7、 Unversity 9q %Z Stalling 7 RF7 S ,1 7i T Annulment T L1s (K ), |hX | 7 ; 5 , I 9S Bypass path V L | 7 1 7WB 2004-11-14 Liping zhang, Tsinghua Unversity 10CMP Hardware Solution 1: Stalling_5i “stall” L IF, RF 2 i O NOPs IRALUi i + 1 i + 5 i + 6 ADD CMP MUL ADD CMP CMP ADD NOP1NOP2ADD NOP1NOP2IFRFWBM
8、UL CMP CMP MUL SUB MUL SUB MUL ALUADD(r1, r2, r3)CMPLEC(r3, 5, r0)MUL(r1,r2,r4)ADD writes r3r3 readi + 2 i + 3 i + 4 R3 “stale”correctCMP stalled on r3“stale”i : iM !2004-11-14 Liping zhang, Tsinghua Unversity 114-Stage L : StallingALUInstructionMemoryADDataMemoryARDWDR/WA BRegisterFileRA1RD1 RD2RA2
9、+4+PCIF1 0 10010 1 24 3 2 1 0WrRA2SELBSELASELWDSELALUFNPCSELZJT00+ 4+ 4Cra rb rcCPCRFIRRFPCALUIRALUA BPCWBIRWBYDALUDWBXPrcIFRFALUWB01“StallRF”IRALUFrom IRRFADD(R31,R31,R31) IRALU NOP PC IRRFF2004-11-14 Liping zhang, Tsinghua Unversity 12Stalling: N ? s K HW qF NOPsE B“ V z qY Ir P q L , 9 V$ 1 WBi :
10、 ? s Stall B E ? P H! m2004-11-14 Liping zhang, Tsinghua Unversity 13Stalling: e StallRF 8 : IRRF, IRALU, and IRWB 7 V % _t7i ra, rb, and rcW1 : Bt P StallRF=1 Hq ( (IRRF.ra = IRALU.rc) | (IRRF.ra = IRWB.rc) ) instr. in RF is reading ra from data being written by instr. in ALU or WB ( (IRRF.opcode !
11、= OPC) & (IRRF.rb = IRALU.rc) | (IRRF.rb = IRWB.rc) similar check for rb, but only if instruction in RF is not an OPC-type instruction (otherwise, rb is meaningless) note: T1 7i R31,5A stall2004-11-14 Liping zhang, Tsinghua Unversity 144-Stage Pipeline w/ StallingALUInstructionMemoryADDataMemoryARDW
12、DR/WA BRegisterFileRA1RD1 RD2RA2+4+PCIF1 0 10010 1 24 3 2 1 0WrRA2SELBSELASELWDSELALUFNPCSELZJT00+ 4+ 4Cra rb rcCPCRFIRRFPCALUIRALUA BPCWBIRWBYDALUDWBXPrcIFRFALUWB01“StallRF”IRALUFrom IRRFADD(R31,R31,R31) IRALU NOP PC IRRFF2004-11-14 Liping zhang, Tsinghua Unversity 15H/W Solution # 2:s Annulment5 :
13、 B 7s$ % -X$ |$ q %Z : NOP, qZ : “Annul” the XORCMP SUB BNE XORCMP SUB BNE CMP SUB BNE CMP SUB BNE i i + 1 i + 2 i + 3 i + 4 i + 5 i + 6 IFRFWBADD ADD ADD ADD ALUXORXORCMP CMP PCIFZPCSEL0x100 0x104 0x108 0x10C 0x110010x1002004-11-14 Liping zhang, Tsinghua Unversity 16YV q LC : qIr H NOPsLOOP: CMPLEC
14、(r3, 100, r0)ADD(r1, r2, r3)SUB(r1, r2, r4)BNE(r0, LOOP)NOP()XOR(r31, r31, r3)CMP SUB BNE CMP SUB BNE CMP SUB BNE CMP SUB BNE i i + 1 i + 2 i + 3 i + 4 i + 5 i + 6 IFRFWBADD ADD ADD ADD ALUCMP CMP PCIFZPCSEL0x100 0x104 0x108 0x10C 0x110010x100 ZE : NOPM V$ * .“branchdelayslot”NOPNOPNOP2004-11-14 Lip
15、ing zhang, Tsinghua Unversity 17YVq LC : AnnulmentLOOP: CMPLEC(r3, 100, r0)ADD(r1, r2, r3)SUB(r1, r2, r4)BNE(r0, LOOP) XOR(r31, r31, r3)CMP SUB BNE CMP SUB BNE CMP SUB BNE CMP SUB BNE i i + 1 i + 2 i + 3 i + 4 i + 5 i + 6 IFRFWBADD ADD ADD ADD ALUCMP CMP PCIFZPCSEL0x100 0x104 0x108 0x10C 0x110010x10
16、0 |h XOR , i NOPs(q1 ) d Y !XORNOPNOP2004-11-14 Liping zhang, Tsinghua Unversity 18AnnulmentInstructionMemoryADRegisterFileRA1RD1 RD2RA2+4+PCIF014 3 2 1 0RA2SELPCSEL00+ 4+ 4Cra rb rcC b 7(Q ) qY 1 q T stallingB 5 V pipelined CPU - unpipelined cpu VS I ?“s ”: - f s $ s$ s2004-11-14 Liping zhang, Tsin
17、ghua Unversity 20q %Z #3: Bypass Paths Write-back Delay Problem1T WB $7i i !57i $ , V ?YZ4 -C Bypass PathsXE : V CPU K 7YV7i F“bypass” ( )7i F “forwarding”2004-11-14 Liping zhang, Tsinghua Unversity 21Bypass Paths 0 bypassing H , CMPLEC and MUL ?p R3 Bypassing P VVY ADD CMP MUL ADD CMP ADD CMP MUL A
18、DD CMP MUL i i + 1 i + 3 i + 4 i + 5 i + 6 IFRFALUWBSUB SUB SUB | L R1=3, R2=4ADD(r1, r2, r3)CMPLEC(r3, 5, r0)MUL(r3,r1,r0)ADD r3CMP | r3i + 2 SUB MUL R3ALUoutWDWB(in)? 777? ? ?V ALUout Bypass RF7ADD 79 r1 + r2 7V WDWB RFMUL | r3r3 V2004-11-14 Liping zhang, Tsinghua Unversity 22Bypass Paths (ALU-RF)
19、 4 , TOPCODERF= OP, OPC, . ANDOPCODEALU= OP, OPC, . ANDraRF= rcALU( BSEL mux 9 )ALUA BRegisterFileRA1RD1 RD2RA21 0 10010 1 2RA2SELBSELASELWDSELWA WDIRRFIRALUA BIRWBYCMPLEC(r3, 5, r0)ADD(r1, r2, r3)2004-11-14 Liping zhang, Tsinghua Unversity 23Bypass Paths (WB-RF) 4 , TOPCODERF= OP ANDWERF = 1 AND rb
20、RF= WAALUA BRegisterFileRA1RD1 RD2RA21 0 10010 1 2RA2SELBSELASELWDSELIRRFIRALUA BIRWBYMUL(r3,r1,r0)ADD(r1, r2, r3)RegisterFileWA WDWERF0 1WASELCMPLEC(r3, 5, r0)2004-11-14 Liping zhang, Tsinghua Unversity 244-Stage PipelineALUInstructionMemoryADDataMemoryARDWDR/WA BRegisterFileRA1RD1 RD2RA2+4+PCIF1 0
21、 10010 1 24 3 2 1 0WrRA2SELBSELASELWDSELALUFNPCSELZJT00+ 4+ 4Cra rb rcCPCRFIRRFPCALUIRALUA BPCWBIRWBYDALUDWBXPrcIFRFALUWB5 : !9 . I ?2004-11-14 Liping zhang, Tsinghua Unversity 25I n / :LD(r1, 0, r4)ADD(r1, r4, r5)XOR(r3, r4, r6)LoadsLD ADD XOR LD ADD XOR LD ADD XOR LD ADD XOR i i + 1 i + 4 i + 5 i
22、+ 6 IFRFALUWBr4 writtenr4 read 1 r4 read 2 5 - bypass paths V % r4 |5 ? i + 3 i + 2 2004-11-14 Liping zhang, Tsinghua Unversity 26I n / :LD(r1, 0, r4)ADD(r1, r4, r5)XOR(r3, r4, r6)LoadsLD ADD XOR LD ADD XOR LD ADD XOR LD ADD XOR i i + 1 i + 4 i + 5 i + 6 IFRFALUWBr4 r4 1 r4 | 2Will our previous bypa
23、ss paths fix bothr4 read problems? i + 3 i + 2 R4ALUoutWDWB(in)? 232323? ? ?23V WDWB RFV ALUout BypassRF? ? ,yADD H 1 R4 2004-11-14 Liping zhang, Tsinghua Unversity 27Bypass Paths: 9 XE : EV7i T H , VYZ “data forwarding” i : L ZX 3 V 5 , 1 stalling NOP e.g., LD 71 stall, T “BH 71 ?4 : 4- 5- ) L , V
24、7P 1 1.0 CPI2004-11-14 Liping zhang, Tsinghua Unversity 285-Stage Pipeline( “full bypassing” annulment)ALUInstructionMemoryADData MemoryARDWDR/WABRegisterFileRA1RD1 RD2RA2+4+PCIF1 01010 1 24 3 2 1 0RA2SELBSELBYPASSESWDSELALUFNPCSEL00+ 4+ 4Cra rb rcCPCRFIRRFPCALUIRALUA BPCMEMIRMEMYMEMDALUDMEMrcIFRFAL
25、UWBPCWBIRWBYWBMEMWr012NOPBNE(r31, 0, XP)AnnulIF0210210210BYPASSESASELZJTNOPBNENOPBNENOPBNEA, B, DMUXA, B, DMUXA, B, D MUXA, B, D MUXA, B, DMUXAnnulRFAnnulALUAnnulMEM0DSELBYPASSESWE2004-11-14 Liping zhang, Tsinghua Unversity 29I n / :loop: LD(r1, 0, r4)ADD(r1, r4, r5)XOR(r3, r4, r6)BEQ(r5,loop,r31)MULC(r7,2,r8)T NOP, (A1 ) P B 4-stage L BETA , T BETA1) No stalling, No bypassing, No annulment2) No stalling, Full bypassing, Annulment3) Full stalling, Full bypassing, No AnnulmentP HWK
